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Current Sink from GPIO 3.3 LVTTL

Altera_Forum
Honored Contributor II
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Hello,  

I've designed a circuit to generate step and directoin signals for external stepper motor drivers. The input current for these drviers is "-1 mA" which I believe means I need to sink 1mA of current. Is the FPGA capable of sinking this much current? I have read that it can output up to 24mA but how much can it sink? I did not find this information anywhere. If anyone can help me I would really appreciate it!  

 

My board is a DE2-115 and the output pins are of the GPIO pins using 3.3 volt logic.
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Altera_Forum
Honored Contributor II
126 Views

 

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Is the FPGA capable of sinking this much current? 

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Yes, the output characteristic of FPGA and CPLD I/Os is almost symmetrical. The sink capabilty will be even slightly higher than the source strength. Some numbers can e found in the DC characteristic part of the device data sheet, complete data for individual IO standards and current strength settings can be found in the ibis files.
Altera_Forum
Honored Contributor II
126 Views

Thank you very much.. I suppose my problem is somewhere else!

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