Cyclon III dev board timing problem

[Altera_Forum]

Hello, 

 I'm studying FPGAs by myself based on books and the literature available on the Altera website. I bought a Cyclone III Nios II evaluation kit, I experimented with all the example designs, and the available tutorials.   Now I'm trying to create a design for the LCD from scratch. So I used the test pattern generator in the SOPC builder. The build perfectly works but there seem to be some problems concerning the timing of the design. In TimeQuest I made an sdc file, and noticed that there were a lot of unconstrained paths, so I read that setting input and output delays was necessairy, but I don't really figure out how to calculate the values of those delays, based on the slack value returned by timequest. (If you look in the attached zip file, you'll se that I experimented with input and output delays a bit...)   Any hints how I can solve this problem?   The complete folder of the design is included as a ZIP file.   Sorry that I bother you which such a newbie question...   Thanks for your time! Best,   Hans

[Altera_Forum]

the LCD data looks like it goes through a MAX II device where its demuxed and send to the LCD. you'll want to get setup and hold information for the MAX II RGB inputs and use those for your set input and output delays. 

 this thread has some useful information, the attachment by gee:  http://www.alteraforum.com/forum/showthread.php?t=2328

[Altera_Forum]

Thanks for the reply pancake :p  

The image is clearer now, I only need to look at the flicker that the LCD is producing now. By building the project quartus tells me that all timing requirements are met.   Best,   Hans