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PVanL
Novice
201 Views

Cyclone® 10 GX Avalon streaming Hard IP for PCIe* Design Example

I am building this design example. 

I have two problems: 

ONE: reference to file in modelsim.tcl

do msim_setup.tcl
# ** Error: couldn't read file "./../common/./../../../../pcie_example_design/sim/common/./../../../ip/pcie_example_design/pcie_example_design_MEM/sim/common/modelsim_files.tcl": no such file or directory
# Error in macro ./msim_setup.tcl line 145
# couldn't read file "./../common/./../../../../pcie_example_design/sim/common/./../../../ip/pcie_example_design/pcie_example_design_MEM/sim/common/modelsim_files.tcl": no such file or directory
# while executing
# "source [file join [file dirname [info script]] ./../../../ip/pcie_example_design/pcie_example_design_MEM/sim/common/modelsim_files.tcl]"
# (file "./../common/./../../../../pcie_example_design/sim/common/modelsim_files.tcl" line 1)
# invoked from within
# "source [file join [file dirname [info script]] ./../../../../pcie_example_design/sim/common/modelsim_files.tcl]"
# (file "./..//common/modelsim_files.tcl" line 1)
# invoked from within
# "source $QSYS_SIMDIR/common/modelsim_files.tcl"

Whatever i do in this file, i can only solve it by typing the direct path instead of reference to SYMDIR. Any idea? 

After solving this, i get SECOND PROBLEM, no idea:

# [exec] file_copy
# ** Error: error copying "../../../../ip/pcie_example_design/pcie_example_design_MEM/altera_avalon_onchip_memory2_180/sim/pcie_example_design_MEM_MEM.hex": no such file or directory
# Error in macro ./msim_setup.tcl line 387
# error copying "../../../../ip/pcie_example_design/pcie_example_design_MEM/altera_avalon_onchip_memory2_180/sim/pcie_example_design_MEM_MEM.hex": no such file or directory
# while executing
# "file copy -force $file ./ "
# ("foreach" body line 1)
# invoked from within
# "foreach file $memory_files { file copy -force $file ./ }"
# ("eval" body line 7)
# invoked from within
# "file_copy"
The file  ip/pcie_example_design/pcie_example_design_MEM/altera_avalon_onchip_memory2_180/sim/pcie_example_design_MEM_MEM.hex does exist, but i assume the reference to this file, just like in msim_setup.tcl, is wrong. I cannot find the file(s) that 'file_copy' is using to determine which files to copy to where.
Please advice.

@Rahul_S_Intel1

0 Kudos
5 Replies
BoonT_Intel
Moderator
194 Views

Hi Sir,

After the design generation, do you change the directory? I am asking this because usually the QSYS_SIMDIR should work one.

I run the same simulation using QII18.0 and I can run the simulation successfully.

 

Maybe you can try to hard code the QSYS_SIMDIR for this line as well.

set memory_files [concat $memory_files [pcie_example_design_tb::get_memory_files "$QSYS_SIMDIR"]]

 

If it still fails, then skip the copy in the tcl, and manually paste the hex file in the mentor directory.

I attach the hex file here.

 

PVanL
Novice
186 Views

Hi BoonT,

Thanks for your reply.

No, i did not change the directory. I tried more variants, like using $QSYS_SIMDIR in the directory string, but whatever level ../i used, it couldn't find the files. I had to use the direct path in line 1, 2, 3,4, of modelsim_files.tcl  under pcie_example_design/sim/common, and only line 1..4.

The copy_files now worked without problem, and without modification other lines of the modelsim_files.tcl

However, pcie_example_bfm_zc3dnuy.sv and pcie_example_design_inst_board_bf_ip_aler_conduit_bfm_zc3dnuy.sv where failing in the directory. I copied them from another project.

I had to modify the modelsim under pcie_a10_hip_0_example_design\ip\pcie_example_design\pcie_example_design_DUT\sim\common\modelsim_files.tcl for some files, but not for all, very strange. See attached modelsim_files.txt Any idea?

Could it be that i specified Cyclone10GX, while the design is made for Arria?

 

regards, Pieter

BoonT_Intel
Moderator
180 Views

Hi Pieter,


I don't understand how you specify C10. Ok, now let's assume you generate the example design using Arria 10 variant. Then after that how you specify C10?

Also, I notice there are some folder hierarchy changed in newer version compare to 18.0. May you can give a try on newer quartus version like 20.1/2.

Anyway, from my side I can run the simulation successfully. I just generate the ED using C10 variant, and just follow the normal flow to run the simulation without changing anything including "specify new device".


Thanks


BoonT_Intel
Moderator
165 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


PVanL
Novice
154 Views

Hi BoonT, i was away for a few days. I have no idea about a C10. I work with the A10. How do you get the C10? I am using the document UG-20234 | 2019.09.19 with Quartus 18.0.

 

What I want to do is: Have a board in the server, send ethernet from server over PCI to ethernet application on FPGA, via transceiver on Cyclone10GX, and back again to the other transceiver on the cyclone10gX, ethernet stack, MAC, PCIexpress, back into the server, and compare if send and received match. Are these the correct settings:

I specified: ( i only touched the first three settings 1, 2, 3)

  1. Interface view: standalone
  2. Example Design: PIO / with Arria 10 GX Development board (there is no Cyclone10GX board, although it does exist, i am told this Arria 10 GX based design also maps onto the Cyclone 10GX development board)
  3. System Settings:
    * App i/f: Avalon-ST
    * Hard IP mode: Gen2x4 / 128 bit / 125 HMz
    * Port type: Native end point
    * RF buffer: Balance
    * RX Buffer completion credits: Header 112, Data 440
  4. PCIe capabilities: 128 byte/32 tags/NONE timeout/disable completion timeout
  5. "configuration, debug and exentio Options":None of hte options under  are marked
  6. PHY characteristics: Gen2 tx de-emphasis: 6dB\
  7. Avalon ST stting: "enable Avalon-ST reset output port
  8. Base Address: Only BAR0: 64 bit prefetchable memory/ 64 kByte - 16 bits