Cyclone 10 GX FPGA (10CX085YF672E6G) IO PINs

[MostafaGhouneem]

I have Cyclone 10 GX FPGA (10CX085YF672E6G). This FPGA has 3V IO bank which supports single ended and differential SSTL ,HSTL, and HSUL I/O standard up to 3V. We want to know if we can use its differential IO as single ended. If yes, can you tell us how can we use its pins (48 pins) as single ended ? Also, can we connect the 48 pins with 48 different signals ?

Thanks

[sstrell]

Just choose a single-ended standard and make the assignment in the Quartus Pin Planner.  Very easy to do.

[AqidAyman_Intel]

Yes, it is correct. You can choose the I/O standard you want to assign to those pins through the Quartus Pin Planner.

Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors.

You can always refer to the I/O Standard Specifications for various I/O standards supported by Intel® Cyclone® 10 GX devices. through the link.

[AqidAyman_Intel]

Hello,

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Thank you.