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Cyclone 10 GX FPGA Development Kit - Bug in Pin Assignments

MatthiasMeyer
Beginner
514 Views

Hello,

we are currently porting a processor design to the Cyclone 10 GX FPGA
Development Kit.

In so doing, I think we detected a bug regarding the pin assignments for
the USER-LEDs in the schematic as well as the golden_top design.

In the golden top, the assignments are as follows:

set_location_assignment PIN_AC7 -to user_led[3]
set_location_assignment PIN_AC6 -to user_led[2]
set_location_assignment PIN_AE6 -to user_led[1]
set_location_assignment PIN_AF6 -to user_led[0]

In the board schematic C10_GX_DK_Rev_A1_Release.pdf, the same
assignments are used, so the golden top and the schematic are
consistent. Unfortunately, the user guide itself does not specify pin locations.

However, these assignments seem to be incorrect. To make our design
work, we had to change it to

set_location_assignment PIN_AC7 -to user_led[3]
set_location_assignment PIN_AF6 -to user_led[2]
set_location_assignment PIN_AE6 -to user_led[1]
set_location_assignment PIN_AC6 -to user_led[0]

So it seems the pins for led[0] and led[2] are swapped.

Can you confirm this bug, and - more importantly - are you aware of
any further bugs regarding the documentation of this board?

Regards,

Matthias.

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1 Solution
Nurina
Employee
463 Views

Hello,


There is no bug in pin assignments. The positions of LED[0] & LED[2] are swapped on the board so this has caused confusion.

As we know from Table 13 of the user guide, the board reference of the USER_LED sequence are as follows:

D22: USER_LED3

D19: USER_LED0

D20: USER_LED1

D21: USER_LED2

User guide here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-gx-fpga-devl-kit.pdf


And the pin locations corresponding to these board references are as follows:

D22 (LED3): AC7

D19 (LED0): AF6

D20 (LED1): AE6

D21 (LED2): AC6


If you look at the board, you can see that the positions of LED2 & LED0 are swapped and the sequence are just like above.

I hope this clarifies your confusion.


Regards,

Nurina


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4 Replies
Nurina
Employee
470 Views

Hello,


Thank you for using Intel Communities.

Please allow some time while I investigate your problem.


Regards,

Nurina


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Nurina
Employee
464 Views

Hello,


There is no bug in pin assignments. The positions of LED[0] & LED[2] are swapped on the board so this has caused confusion.

As we know from Table 13 of the user guide, the board reference of the USER_LED sequence are as follows:

D22: USER_LED3

D19: USER_LED0

D20: USER_LED1

D21: USER_LED2

User guide here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-gx-fpga-devl-kit.pdf


And the pin locations corresponding to these board references are as follows:

D22 (LED3): AC7

D19 (LED0): AF6

D20 (LED1): AE6

D21 (LED2): AC6


If you look at the board, you can see that the positions of LED2 & LED0 are swapped and the sequence are just like above.

I hope this clarifies your confusion.


Regards,

Nurina


MatthiasMeyer
Beginner
450 Views

Hello Nurina,

thank you very much for the detailed and helpful response.

I did not expect this counter-intuitive numbering of the leds on the board.

Thanks again,

Matthias.

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Nurina
Employee
440 Views

Hello Matthias,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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