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OlegT
New Contributor I
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Cyclone 10 GX FPGA Development Kit - PCIe AvalonMM-DMA example

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Hello.

I use AN829 as starting point of my design.

In Platform Builder I see, that PCIe hip is connected to DDR3 emif via avalon MM bus.

Both components use different clock sources, but they are connected directly.

I expect that "Avalon-MM Clock Crossing Bridge" should be used here, but the design works well without it.

Please explain, in which situations I have to use this bridge, and in which not.

Thank you.

Best regards,

Oleg.

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1 Solution
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Hi Oleg,

 

Thanks for your patience while I was checking the design.

 

If you refer to the Platform Designer: Interconnect Requirements, there are some settings that allow the software to automatically insert the clock crossing adapters and add pipeline stages to the Platform Designer interconnect when you generate a system.

 

In our case, the clock crossing adapter type is set to FIFO and maximum pipeline stages is set to 4.

Capture.JPG

Thanks

Best regards,

KhaiY

 

View solution in original post

6 Replies
282 Views

Hi Oleg,


Please allow me some time to check on this.


Thanks

Best regards,

KhaiY


238 Views

Hi Oleg,


The Clock Crossing Bridge allows pipelined read masters to post multiple reads to the bridge even if the slaves downstream from the bridge do not support pipelined transfers. Before using the clock crossing bridges in your design, you should

carefully consider their effects. The bridges can have any combination of the following effects on your design:

  • Increased Latency - it has an effect on the read latency between the master and the slave.
  • Limited Concurrency - Placing a bridge between multiple Avalon-MM master and slave ports limits the number of concurrent transfers your system can initiate.
  • Address Space Translation - The slave port of a pipeline or clock crossing bridge has a base address and address span.


Thanks

Best regards,

KhaiY


OlegT
New Contributor I
236 Views

Why it is not used in  PCIe AvalonMM-DMA example?

218 Views

Hi Oleg,

 

Thanks for your patience while I was checking the design.

 

If you refer to the Platform Designer: Interconnect Requirements, there are some settings that allow the software to automatically insert the clock crossing adapters and add pipeline stages to the Platform Designer interconnect when you generate a system.

 

In our case, the clock crossing adapter type is set to FIFO and maximum pipeline stages is set to 4.

Capture.JPG

Thanks

Best regards,

KhaiY

 

View solution in original post

OlegT
New Contributor I
190 Views

Thanx!

182 Views

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


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