FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6353 Discussions

Cyclone 10 LVDS on DIFFCLK lines

Ms_G
Novice
705 Views

HI,

Can I use DIFFCLK_[0..7]p and DIFFCLK_[0..7]n pairs as LVDS input pins on Cyclone 10 LP device?

Thanks

Labels (1)
0 Kudos
5 Replies
FvM
Honored Contributor II
680 Views
Hi,
according to my reading of pinout table, it's not possible.
0 Kudos
Ms_G
Novice
667 Views

Thanks FvM, Can I use atleast as Input pins to read push buttons or dip switches. 

0 Kudos
FvM
Honored Contributor II
649 Views

Yes, free clock inputs can be used as single ended inputs. Other than regular IO they don't provide weak-pullup resistors for unused pins, thus unused clocks should be connected to ground, as stated in pin connection guideline and Quartus .pin file.

0 Kudos
Ms_G
Novice
643 Views

Thanks, Much appreciated.

0 Kudos
AqidAyman_Intel
Employee
611 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


0 Kudos
Reply