I have connected Cylone 10 lp (10CL10YU25617G) pin A14 i.e usually an I/O but in optional case it act as a PLL2_CLKOUTn but i am using it as an I/O. the problem is that this pin ties always high it didnt pull down. i am using this pin as as a bidirectional pin to configure the SDRAM. my question is why it always high and what is its normal state of that pin tri state / high or low?
Maybe that is part of configuration sequence. Please refer to page 146 of this document: https://www.intel.co.jp/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf
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