Cyclone 10GX dev kit PCIe example

[Altera_Forum]

I downloaded this example design for the Cyclone 10GX dev kit at:https://cloud.altera.com/devstore/platform/2151/download/ 

  and extracted the archive. But if I load the enclosed sof file:   md5sum Cyclone10GX_PCIeGen2x4_DMA_17_1_2_restored/master_image/top.sof 726940bdd434031299372ceeb1cae16e Cyclone10GX_PCIeGen2x4_DMA_17_1_2_restored/master_image/top.sof And re-boot the PC in which the PCIe board is installed the PC will not even boot. It will not boot until I power cycle the PC (in which the loaded sof file disappears of course). I have no problems booting and enumerating using other PCIe boards inserted into the same PCIe slot on the PC. The PC has an Intel H270 Express chipset.   Did anybody else get the example PCIe design enumerated and accessible? Or even got the DMA example running?

[Altera_Forum]

Hi Petter, 

 I'm experiencing the same problem. Have you been able to get the PCIe example running?  Thanks, Petr

[Altera_Forum]

Hi Petr, 

 Unfortunately not. The reply I got from Altera was basically a reference to   https://www.altera.com/en_us/pdfs/literature/ug/ug-dex-a10-pcie-avst.pdf (1)   Which means introducing even more potential errors when designing the PCIe app and assigning pins/constraints myself. I was hoping for a working PCIe design in order to prove that my board and SW works (at least lspci and config space access). Then I could develop my own app from there.  I also downloaded Quartus 18. But the example dev kit options for the PCIe HIP in Quartus 18 is only Arria 10 or None.   1) This seem to be a bit out of date as it states on page 3: "Note: Intel Cyclone 10 GX dvelopment kits are not yet available."

[Altera_Forum]

Hi Petter, 

 It turned out the design is somehow broken. Anyway there is possibility to generate example design in PCIe core, so I tried that way and beside the compilation took half the time, the system booted and lspci showed the card. I'm going to try user space test app.  Regards  # lspci -vv 01:00.0 Non-VGA unclassified device: Altera Corporation Device e003 (rev 01)  Physical Slot: 0  Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-  Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-  Interrupt: pin A routed to IRQ 255  Region 0: Memory at b2002000 (64-bit, prefetchable)   Region 2: Memory at b2000000 (64-bit, prefetchable)   Capabilities: [50] MSI: Enable- Count=1/4 Maskable- 64bit+  Address: 0000000000000000 Data: 0000  Capabilities: [78] Power Management version 3  Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-  Capabilities: [80] Express (v2) Endpoint, MSI 00  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us  ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-  RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+  MaxPayload 256 bytes, MaxReadReq 512 bytes  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-  LnkCap: Port# 1, Speed 5GT/s, Width x4, ASPM not supported, Exit Latency L0s <4us, L1 <1us  ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+  ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-  LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-  DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-  Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-  Compliance De-emphasis: -6dB  LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-  EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-  Capabilities: [100 v1] Virtual Channel  Caps: LPEVC=0 RefClk=100ns PATEntryBits=1  Arb: Fixed- WRR32- WRR64- WRR128-  Ctrl: ArbSelect=Fixed  Status: InProgress-  VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-  Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-  Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff  Status: NegoPending- InProgress-  Capabilities: [200 v1] Vendor Specific Information: ID=1172 Rev=0 Len=044 <?>  Capabilities: [800 v1] Advanced Error Reporting  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+  AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-  Kernel driver in use: altera-cvp  Kernel modules: altera_cvp  # rmmod altera_cvp # insmod altera_dma.ko # dmesg  [ 4369.485406] Altera DMA: altera_dma_init() [ 4369.485441] Altera DMA 0000:01:00.0: enabling device (0000 -> 0002) [ 4369.485573] Altera DMA 0000:01:00.0: pci_enable_device() successful [ 4369.485633] Altera DMA 0000:01:00.0: pci_enable_msi() successful [ 4369.485639] Altera DMA 0000:01:00.0: using a 64-bit irq mask [ 4369.485641] Altera DMA 0000:01:00.0: irq pin: 1 [ 4369.485642] Altera DMA 0000:01:00.0: irq line: 255 [ 4369.485644] Altera DMA 0000:01:00.0: irq: 135 [ 4369.485645] Altera DMA 0000:01:00.0: request irq: 255 [ 4369.485648] Altera DMA 0000:01:00.0: BAR[0] 0xb2002000-0xb20021ff flags 0x0014220c, length 512 [ 4369.485650] Altera DMA 0000:01:00.0: BAR[1] 0x00000000-0x00000000 flags 0x00000000, length 0 [ 4369.485652] Altera DMA 0000:01:00.0: BAR[2] 0xb2000000-0xb2001fff flags 0x0014220c, length 8192 [ 4369.485654] Altera DMA 0000:01:00.0: BAR[3] 0x00000000-0x00000000 flags 0x00000000, length 0 [ 4369.485657] Altera DMA 0000:01:00.0: BAR[4] 0x00000000-0x00000000 flags 0x00000000, length 0 [ 4369.485658] Altera DMA 0000:01:00.0: BAR[5] 0x00000000-0x00000000 flags 0x00000000, length 0 [ 4369.485675] Altera DMA 0000:01:00.0: BAR[0] mapped to 0x00000000ba380ab7, length 512 [ 4369.485683] Altera DMA 0000:01:00.0: BAR[2] mapped to 0x000000008a16e315, length 8192

[Altera_Forum]

When I tried to start the test, the driver crashed. 

My test system is Ubuntu 18.04 with kernel 4.15 so the crash could be caused by that. I'll look deeper into the driver and design.  [ 4656.163395] BUG: unable to handle kernel paging request at ffffb38e819d0000 [ 4656.163420] IP: iowrite32+0x1e/0x40 [ 4656.163426] PGD 45d142067 P4D 45d142067 PUD 0  [ 4656.163441] Oops: 0002 [#1] SMP PTI [ 4656.163447] Modules linked in: altera_dma(OE) sep4_1(OE) socperf2_0(OE) pax(OE) nls_iso8859_1 snd_soc_skl snd_soc_skl_ipc snd_hda_ext_core snd_soc_sst_dsp snd_soc_sst_ipc snd_soc_acpi snd_soc_core snd_hda_codec_hdmi snd_compress snd_hda_codec_realtek snd_hda_codec_generic ac97_bus intel_rapl snd_pcm_dmaengine snd_hda_intel x86_pkg_temp_thermal snd_hda_codec intel_powerclamp coretemp snd_hda_core snd_hwdep kvm_intel snd_pcm kvm snd_seq_midi snd_seq_midi_event irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_rawmidi pcbc snd_seq aesni_intel input_leds snd_seq_device aes_x86_64 snd_timer crypto_simd glue_helper cryptd intel_cstate intel_rapl_perf snd mei_me intel_wmi_thunderbolt mei fpga_mgr intel_pch_thermal soundcore shpchp sch_fq_codel mac_hid acpi_pad parport_pc ppdev lp parport ip_tables [ 4656.163574] x_tables autofs4 hid_generic usbhid hid i915 drm_kms_helper igb e1000e syscopyarea sysfillrect sysimgblt dca fb_sys_fops i2c_algo_bit ahci ptp drm pps_core libahci wmi video pinctrl_sunrisepoint [last unloaded: altera_cvp] [ 4656.163627] CPU: 3 PID: 2392 Comm: user Tainted: G OE 4.15.0-22-generic# 24-Ubuntu [ 4656.163633] Hardware name: DFI Inc. KU17x/KU17x, BIOS B17C.15A 12/15/2017 [ 4656.163641] RIP: 0010:iowrite32+0x1e/0x40 [ 4656.163647] RSP: 0018:ffffb38e4244bd80 EFLAGS: 00010292 [ 4656.163654] RAX: 0000000000000000 RBX: ffffb38e819d0000 RCX: 0000000000000000 [ 4656.163661] RDX: 0000000000000040 RSI: ffffb38e819d0000 RDI: 0000000060109915 [ 4656.163667] RBP: ffffb38e4244bd80 R08: ffffb38e4244bcf8 R09: ffffb38e4244bcf8 [ 4656.163672] R10: 00000000a7509d81 R11: 000000006b9b0bd0 R12: 0000000040000004 [ 4656.163678] R13: ffff999c5a382000 R14: 0000000040000800 R15: ffff999c2f200800 [ 4656.163685] FS: 00007fd863fda500(0000) GS:ffff999c6dd80000(0000) knlGS:0000000000000000 [ 4656.163692] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4656.163697] CR2: ffffb38e819d0000 CR3: 000000042a9ce006 CR4: 00000000003606e0 [ 4656.163703] Call Trace: [ 4656.163721] init_ep_mem.constprop.13+0x5a/0x90 [altera_dma] [ 4656.163732] altera_dma_ioctl+0x4ed/0xe20 [altera_dma] [ 4656.163744] ? do_wait_intr_irq+0x90/0x90 [ 4656.163757] do_vfs_ioctl+0xa8/0x630 [ 4656.163769] ? vfs_read+0x115/0x130 [ 4656.163780] SyS_ioctl+0x79/0x90 [ 4656.163791] do_syscall_64+0x73/0x130 [ 4656.163803] entry_SYSCALL_64_after_hwframe+0x3d/0xa2 [ 4656.163810] RIP: 0033:0x7fd863af15d7 [ 4656.163816] RSP: 002b:00007ffe48631e18 EFLAGS: 00000207 ORIG_RAX: 0000000000000010 [ 4656.163824] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fd863af15d7 [ 4656.163829] RDX: fffffffffffff38d RSI: 0000000000006601 RDI: 0000000000000003 [ 4656.163835] RBP: 00007ffe48631e80 R08: 00007ffe48631e51 R09: 0000000000000000 [ 4656.163840] R10: 00007fd863b79cc0 R11: 0000000000000207 R12: 0000558c2cfdfae0 [ 4656.163846] R13: 00007ffe48631f60 R14: 0000000000000000 R15: 0000000000000000 [ 4656.163853] Code: 5d c3 90 66 2e 0f 1f 84 00 00 00 00 00 55 48 81 fe ff ff 03 00 48 89 e5 77 11 48 81 fe 00 00 01 00 76 0c 0f b7 d6 89 f8 ef 5d c3 <89> 3e 5d c3 48 89 f7 48 c7 c6 76 5f f1 9e e8 5f fe ff ff 5d c3  [ 4656.163973] RIP: iowrite32+0x1e/0x40 RSP: ffffb38e4244bd80 [ 4656.163977] CR2: ffffb38e819d0000 [ 4656.163985] ---[ end trace 29297b63cb0dbe98 ]---

[Altera_Forum]

Great to hear. Did you use the Arria 10 example or the None example as a base for your design? 

 Would you care to share the sof? Then I can at least test my board and PC. If it works I know I should be able to re-produce.

[Altera_Forum]

Also which Quartus version did you use?

[Altera_Forum]

Hi Petter, 

 I've used None example as a base. Quartus pro 17.1.2.  Regarding sof file, unfortunately I did not archive it, so just build the example and load it to the board, hopefully it will work. I'm extending design with PIO IP connected to user LEDs to have something simple to test. As I'm software guy, I do not understand all the magic with quartus, but I'm learning.  Regards, Petr

[Altera_Forum]

Thank you for your reply. I will try the None design as a base.

[Altera_Forum]

Got endpoint detected using lspci even though I'm just using 1x gen1 for now. At least the PC is booting...

[Altera_Forum]

Hi Petter, 

 Good to see it somehow works for you. I tested it on Gen2. I have not progress so far, so I'm putting it on ice until our FPGA guy has time.  I checked the Altera site and found new design for Quartus 18.0.0, so I'll test it whether it works.  Regards, Petr

[Altera_Forum]

Hi Petter, 

 Bummer, it does not work either.  What I'm curious about is why Cyclon 10 devboard is not listed when example design is generated from PCIe IP core?  Regards, Petr

[Altera_Forum]

Just a thought, have you got it in a PCIe slot that can provide 75W of power?

[Altera_Forum]

Hi Stephen, Petter, 

 As I already wrote, I'm SW guy without knowledge of all FPGA magic. But once our FPGA guy created simple test design from scratch, it worked just fine.  My problem was probably related to the fact I didn't know that BAR2 and BAR3 is reserverd for configuration of DMA controller and I used them for another purpose. Probably due some conflict it failed to boot. Why reference design didn't work at all is probably different story.  Regards, Petr

[Jose_G_Intel3]

Hello All,

Im having a similar issue. Have you find a solution for this issue yet?