Cyclone II EP2C35 - SOF downloaded but doesn't run

[Altera_Forum]

Hi, 

 I am using Quartus II 8.0 with the nios ii development kit, cyclone ii edition (http://www.altera.com/products/devkits/altera/kit-nios-2c35.html). I created a very simple hardware design like in my-first-fpga-tutorial. Then I compiled and downloaded it. But when the download is finished, the factory default program begins to run (instead of my hardware design).   I searched with google and in this forum but I couldn't find an answer.   Can anyone explain why the factory default runs and not my hardware design?   Regards, Stefan

[Altera_Forum]

Hi Stefan, 

I understand that you are downloading just a Quartus program, without NIOS. When you reset your Kit (with reset button or power off) the EPCS download the configuration that it has saved in memory to the FPGA, and you lost your old configuration (The FPGA is "volatyle", the Hardware configuration is lost when you switch off). You have tried to download and test it without reset or power off? it must work, just to check it.   I'm not sure how to fix a quartus program to a EPCS IC without NIOS, I suppose that you will need to use the SOPC Builder to create a EPCS connection and flash it.    I have the same Kit, I will try to check and help you.   Regards.   Isaac Campos

[Altera_Forum]

--- Quote Start ---   But when the download is finished, the factory default program begins to run (instead of my hardware design).  --- Quote End ---    As he wrote, after the download the wrong image starts. if you download an image with quartus programmer for example, then the fpga starts with this image. now he says the old image is used, so i assume that he downloads the old (already programmed) image. do you have a web edition ? have a look at the files. if you use a web edition the sof file name has "time_limited" or something like that in addition to the file name. so check if you create a time limited sof but programm the non time limited sof file.

[Altera_Forum]

--- Quote Start ---  I understand that you are downloading just a Quartus program, without NIOS.  --- Quote End ---     That's right.     --- Quote Start ---  When you reset your Kit ...  --- Quote End ---   No, I did not press reset or turned power off. I programmed it, and when the progress bar in Quartus Programmer reached 100% some LEDs started blinking and the factory default image started.       --- Quote Start ---  I have the same Kit, I will try to check and help you.  --- Quote End ---     Thank you. :)      --- Quote Start ---  now he says the old image is used, so i assume that he downloads the old (already programmed) image.  --- Quote End ---     I don't think so. It's strange, because in the Quartus-project called "NiosII_cycloneII_2c35_standard" there is no problem, I can compile and download it and it runs. But my new project doesn't run.     --- Quote Start ---  do you have a web edition ?  --- Quote End ---     No, I have: quartus ii version 8.0 build 215 05/29/2008 sj full version     Maybe there is a specific option / setting for this problem in Quartus ... ?

[Altera_Forum]

even if the project is called MyProject and normaly it would generate a MyProject.sof, but if you loose your licence for any circustance the same system would generate a MyProject _time_limited.sof (something like that) and leave the MyProject.sof untouched.  

i had this a couple of times and it took each time a couple of compile and programm to find out that quartus now generates a time limited sof. but you will see such an sof file in your project folder if it exists  if the sof you try to programm is broken, the programmer would tell you that and the config done pin wouldn't tell you that the configuration was successful. so if the configuration is successful but it is the wrong image then there are 2 possabilities. the fpga is configured via jtag but with the wrong image, or the fpga is not configured via jtag but via on board configuration with the old image. so could you delete the on board configuration image or bring the board into a mode where it does not configure itself from epcs or cfi.  does the same problem exists when you configure via command line ?

[Altera_Forum]

--- Quote Start ---  if the sof you try to programm is broken, the programmer would tell you that and the config done pin wouldn't tell you that the configuration was successful.  --- Quote End ---     If I use a good SOF-File, the error LED is on while programming, then it get's off and the Config Done LED is on and the fpga-program runs.   If I use my non-working SOF-File, it's the same but the Config Done LED is only on for a few millisceonds. Then the Flash_CE_n LED is on and the FPGA loads the factory image.       --- Quote Start ---  or the fpga is not configured via jtag but via on board configuration with the old image. so could you delete the on board configuration image or bring the board into a mode where it does not configure itself from epcs or cfi.  --- Quote End ---     In theory, I could delete the on board configuration image or change the mode. But the question is, why some SOF-Files are working and some not.     --- Quote Start ---  does the same problem exists when you configure via command line ?  --- Quote End ---     I don't know how to do that. I guess you don't mean the NIOS II Command Shell, because I'm not working with NIOS.     Maybe the problem is related to a pll function in my design. I use ALTPLL from MegaWizard Plug-In Manager. And because my FPGA is EP2C35F672C6N, I can't select speed 8 in this block, I think. It's still not working, I think that the problem is because of the PLL function. So I removed the pll but it did not help...

[Altera_Forum]

i don't think it is big difference that you use a c6 and can't select c8 in a working or non working image 

 but you wrote that the Conf Done LED is on for a few mSec. could it be that this board is reconfigured by a watchdoch or a fpga pin ? maybe you use a pin a bit different than the working sof  i am unshure about the reconfiguration option due to an error that is avaiable in quartus settings.

[Altera_Forum]

--- Quote Start ---   could it be that this board is reconfigured by a watchdoch or a fpga pin ? maybe you use a pin a bit different than the working sof.  --- Quote End ---   Yes...   Finally I found the solution for this problem:   quartus menu assignments > device > device and pin options... > unused pins > Reserve all unused pins: as input tri-stated   (Before it was set to as output driving ground.)   That is mentioned in the my first fpga tutorial:     --- Quote Start ---  For Cyclone III devices, unused I/O pins default to tri-stated inputs. You can change this setting using the unused pins tab in the device and pin options dialog box. Refer to Quartus II Help for more information about this option and how to use it.   --- Quote End ---     This morning I already read that, but I thought that it was not important and I wanted to get on fast. Now I spent the whole day finding this simple error/bug. So we can see, that one should always work unhurriedly.   So, thank you, MSchmitt! :)