FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5152 Discussions

Cyclone III 3C120 Development Board, the other Clock!

Altera_Forum
Honored Contributor II
763 Views

Have one cuestion when load the NIOS processor inside the FPGA only appear available the clock of 50 Mhz, but the board have another of 125 MHz why can't use that?:) 

 

 

On-board clocking circuitry 

■ Two clock oscillators to support Cyclone III device user logic 

■ 50 MHz 

■ 125 MHz
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
107 Views

the 125Mhz is generate by phy.  

this clock only works if you take out the reset the phy chip . you can use this clk but you need take care. 

 

Franz Wagner
Altera_Forum
Honored Contributor II
107 Views

No it's not generated by the PHY, it's a regular oscillator. Have a look at page 7 of the schematics. 

You can use it if you want, it's connected to the A14 pin on the FPGA.
Altera_Forum
Honored Contributor II
107 Views

 

--- Quote Start ---  

No it's not generated by the PHY, it's a regular oscillator. Have a look at page 7 of the schematics. 

You can use it if you want, it's connected to the A14 pin on the FPGA. 

--- Quote End ---  

 

 

What is the risk of activate this clock? :(
Altera_Forum
Honored Contributor II
107 Views

There is no risk. It is indeed an oscillator supposed to feed the PHY but you can also use it for other things in your FPGA. Alternatively you can also use a pll on the 50MHz clock to generate other frequencies

Reply