Hello,I have got the DK-DEV-3C120N kit. (see http://www.altera.com/products/devkits/altera/kit-cyc3.html). I was wondering if there is any possibility to get the source code of the design in the MAX II device, which is responsible for programming the Cyclone III from flash. My issue is, that the MAX II will block the external JTAG connector (J14) as long as it is enabled (SW3 MAX_ENABLE is 0). The reason is that the MAX II will drive to the JTAG pins of the Cyclone III device. So the MAX II will drive against the signals from the external JTAG connector. I think it should be trivial to modify the MAX II design to tri-state the JTAG signals to the Cyclone III, if the DEV_SEL jumper is NOT plugged (DEV_SEL is high). To implement this modification I would need the source code of the MAX II design... with best regards Ingo Rohloff
According to the reference manúal, you have the option to use an external USB Blaster to connect either to the FPGA or the MAX II, see Table 2-7. Obviously, it would be the most versatile solution to have the MAX II source. I fear, Altera don't wan't to disclose it.
--- Quote Start --- According to the reference manúal, you have the option to use an external USB Blaster to connect either to the FPGA or the MAX II, see Table 2-7. Obviously, it would be the most versatile solution to have the MAX II source. I fear, Altera don't wan't to disclose it. --- Quote End --- I wonder why Altera doesn't disclose at least the protocol. Is it just some kind of nonsense policy to protect every possible IP? Or may be it has something to do with Terasic? Conceivable Terasic developed the USB Blaster, and Altera has some kind of agreement?
I think, that the USB Blaster has been produced by Altera first, but I may be wrong. If you are interested to use the USB Blaster protocol, either to access an USB Blaster from your own PC application or to design a compatible embedded USB Blaster, you'll find independend sources on the internet. The protocol isn't that complicated and can be decoded by watching USB Blaster operation.Best regards, Frank
--- Quote Start --- I think, that the USB Blaster has been produced by Altera first, but I may be wrong. ... --- Quote End --- Argh. I totally forgot, that the Max II does contain some logic, which implements an USB Blaster. I always use an external one... (To be precise I use a Lauterbach debugger to connect to the Cyclone III.) What I am interested in is the flash loader part of the Max II. (So the part which configures the Cyclone III from a design which resides in the FLASH of the board.) With the current Max II design (1337 revision) you have to disable the Max II completely to use an external USB blaster. This means that if you want to use an external USB blaster, the flash loader of the Max II does not work any longer (because you have to disable the Max II completely). A trivial solution would be to disable the drive of the MAX II onto the Cyclone III JTAG pins as soon as the DEV_SEL jumper is removed. (The Max II is connected to the DEV_SEL signal and thus can read it out.) with best regards Ingo PS: Of course you can implement your own Flash loader design for the Max II by using some example Altera Design, but it really would be nice if this would work out of the box.