Re: Cyclone III FPGA Starter transer data

Altera_Forum · ‎03-14-2010

I wrote simple project (digital filter), I programmed Cyclone III FPGA Starter device and now I want to transfer some data to my filter via USB and receive them. How can I do that? I need to write a module in order to communicate with USB or what? I'm really beginner in using development kits.

My filter has these I/O :


LIBRARY IEEE; 
USE IEEE.std_logic_1164.all; 
USE IEEe.std_logic_arith.all; 
USE IEEE.std_logic_signed.all; 
ENTITY filtr_fir_latwy IS 
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(27 downto 0);
         filter_out                      :   OUT   std_logic_vector(43 downto 0);  
         enable                      :    OUT   std_logic 
         ); 
END filtr_fir_latwy;

How can I send 28 bits data and receive 44 bits? How should I connect clock signal to clk port? I will be very appreciate for every answer.

Altera_Forum · ‎03-18-2010

You should look at the Virtual JTAG Megafunction (sld_virtual_jtag). I was able to get data into and out of my starter kit using it.