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Altera_Forum
Honored Contributor I
1,645 Views

Cyclone III Starter Kit - DDR-SDRAM - help

I'm newbie user in FPGA and I need to read and to write in DDR-SDRAM from Cyclone III starter kit. 

 

I altered the QB3 example (.bdf). 

And I created a new project in Nios II loading the .ptf file from cycloneIII_3c25_start_niosII_standard_sopc.ptf. 

 

I program a little code for test, bu I don't have success. 

 

Somebody can help me ? 

 

Thanks 

 

Rester
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12 Replies
Altera_Forum
Honored Contributor I
103 Views

What exactly does not work? Are there any error messages? Did you try the "Hello NIOS" example and does it run correctly? I`m not sure if the SDRAM is connected in the standard_sopc file. If it is the NIOS CPU use it to store your data or code in it. So you can write something into RAM by writing something like: 

 

int a = 42; 

 

Or do you mean something different and I´m sure you do.
Altera_Forum
Honored Contributor I
103 Views

My really question is: 

 

I want to write and to read in ddr-sdram. 

 

I have four options:  

 

*Implement all logic by "hand" (in code VHDL);  

*Use the SOPC Builder for start the project from 'zero'; 

*Change the QB3 Control Painel example; 

*Change the CycloneIII_3c25_start_niosII_standard example. 

 

Changing the QB3 Control Painel example, I don't have the SOPC Builder System PTF file for implement my code in Nios II. And I don't get to create this file. 

 

Changing the CycloneIII_3c25_start_niosII_standard example, my project have only: Nios II processor,DDR-SDRAM controller,jtag,onchip memory and led pio. 

I compile the project, and in the Nios software, I program this code: 

 

 

int main(void) 

 

int ch; 

int a,b,c,d; 

int memory_base = 0x02000000; 

 

/* Print the Header */ 

MenuHeader(); 

/* Print the menu and do what the user requests, until they hit 'q' */ 

while (1) 

IOWR_8DIRECT(memory_base, 0, 0x0A); 

IOWR_8DIRECT(memory_base, 1, 0x05); 

IOWR_8DIRECT(memory_base, 2, 0xA0); 

IOWR_8DIRECT(memory_base, 3, 0x50); 

a = IORD_8DIRECT(memory_base, 0); 

b = IORD_8DIRECT(memory_base, 1); 

c = IORD_8DIRECT(memory_base, 2); 

d = IORD_8DIRECT(memory_base, 3); 

 

printf( "\nmemory 1 = %d.\n",a); 

printf( "\nmemory 2 = %d.\n",b); 

printf( "\nmemory 3 = %d.\n",c); 

printf( "\nmemory 4 = %d.\n",d); 

//ch = TopMenu(); 

if (ch == 'q') 

printf( "\nExiting from Memory Test.\n"); 

break; 

return (0); 

 

But, when I run this, appears a error: 

 

Verifying 02000000 ( 0%) 

Verifying 02010000 (83%) 

Verifying 04001020 (99%) 

Verify failed between address 0x4001020 and 0x40011C7 

Leaving target processor paused 

 

Someone help me ? 

 

Before tihe, I tried to test the memory test template of Nios II and I don't have success too. 

 

 

Altera_Forum
Honored Contributor I
103 Views

PS.: this address error is from the onchip memory, looking the SOPC Builder

Altera_Forum
Honored Contributor I
103 Views

Deleting the on_chip memory, appears: 

 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloading 02010000 (83%) 

Downloaded 78KB in 1.3s (60.0KB/s) 

 

Verifying 02000000 ( 0%) 

Verifying 02010000 (83%) 

Verified OK  

Leaving target processor paused 

 

I really lost now. rs
Altera_Forum
Honored Contributor I
103 Views

Does the hardware design meet timing requirements?

Altera_Forum
Honored Contributor I
103 Views

where I check this ?

Altera_Forum
Honored Contributor I
103 Views

First you must launch Timequest to check that all the I/O are constrained. Then you can either check if the timing requirements are met in Timequest, or by looking at the critical warnings when you compile your Quartus project. 

What changes did you do to the CycloneIII_3c25_start_niosII_standard? I assume the standard example is properly constrained.
Altera_Forum
Honored Contributor I
103 Views

Hi 

 

I faced problem when running CycloneIII_3c25_start_niosII_standard. I have Verify address failed problem. The address is pointing to sdram. Could anyone help? 

 

Thanks
Altera_Forum
Honored Contributor I
103 Views

Try to run a memory test on the sdram, from on-chip memory.

Altera_Forum
Honored Contributor I
103 Views

i tried running memory test template from Nios II. It appears memory bit failed to be verified at data bit 0x01 sort of msg in console. if that's the case, how can i debug it? 

 

thanks, 

caridee
Altera_Forum
Honored Contributor I
103 Views

It looks like a hardware problem on the sdram access. 

Is the sof file the reference one given with the kit, or did you recompile it yourself?
Altera_Forum
Honored Contributor I
103 Views

 

--- Quote Start ---  

It appears memory bit failed to be verified at data bit 0x01 sort of msg in console 

--- Quote End ---  

 

 

I also had this problem once, the cause of this error was the use of a false base adress. When you are, for example, using a clock crossing bridge, you get an absolute and a relative base adress and it is very important to use the absolute base adress in the memtest application. 

 

That solved the problem for me (I'm not a specialist myself, just trying to help...) 

 

There's a picture of the SOPC builder in the attachment that shows what I mean. 

 

Good luck! 

 

Best, 

 

Hans
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