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Valued Contributor III
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Cyclone III Starter Kit - JTAG programming

Has anyone been able to program (i.e. download a design) using the JTAG interface located in J4? The USB blaster interface seems to be working just fine, but when I populated the J4 connector I get a download failure. I'm using Quartus II V7.2. 

 

I contacted Altera about this and they replied that there is a *known* issue are investigating. 

 

Any help is appreciated, thanks in advance,
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Valued Contributor III
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I am having the same issue currently. Would you mind to share how you solve this issue finally? Thanks in advance!

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Valued Contributor III
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hello, 

 

i did finally get this to work, you have to shorten the JP8 and keep the USB-Cable 

connected between computer and the dev. kit. this was a *very* slow download, 

so i just started using the usb exclusively. unfortunately, this was a long time ago 

so i don't remember anymore details off hand.
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Valued Contributor III
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--- Quote Start ---  

hello, 

 

i did finally get this to work, you have to shorten the JP8 and keep the USB-Cable 

connected between computer and the dev. kit. this was a *very* slow download, 

so i just started using the usb exclusively. unfortunately, this was a long time ago 

so i don't remember anymore details off hand. 

--- Quote End ---  

 

 

Unfortunately, I already shunt the JP8, but not avail :( . Everything still not going well. What is your board part number? My board is 6xx-4133R-0B. 

By the way, may I know how you communicate with Altera in the earlier stage? Did you file SR? May I know the SR#. I wish to file another so that they can look into it. 

Thanks for giving a helping hand.:)
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Valued Contributor III
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--- Quote Start ---  

Unfortunately, I already shunt the JP8, but not avail :( . Everything still not going well. What is your board part number? My board is 6xx-4133R-0B. 

By the way, may I know how you communicate with Altera in the earlier stage? Did you file SR? May I know the SR#. I wish to file another so that they can look into it. 

Thanks for giving a helping hand.:) 

--- Quote End ---  

 

 

>What is your board part number? My board is 6xx-4133R-0B. 

the board part number i purchased is "DK-START-3C25N" 

 

>Did you file SR? May I know the SR#. 

yes. sr# 10620653
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Valued Contributor III
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--- Quote Start ---  

>What is your board part number? My board is 6xx-4133R-0B. 

the board part number i purchased is "DK-START-3C25N" 

 

>Did you file SR? May I know the SR#. 

yes. sr# 10620653 

--- Quote End ---  

 

 

Thanks a lot! i am going to file another SR because I could not get it done.:mad:
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Valued Contributor III
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You didn't tell what adapter you connected when trying to program through J4. An USB Blaster?

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Valued Contributor III
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--- Quote Start ---  

You didn't tell what adapter you connected when trying to program through J4. An USB Blaster? 

--- Quote End ---  

 

 

no, a byteblaster-ii... (but the usb *must* be plugged in anyway.)
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Valued Contributor III
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--- Quote Start ---  

You didn't tell what adapter you connected when trying to program through J4. An USB Blaster? 

--- Quote End ---  

 

 

Ya, I am using USB blaster Rev C and try to access the J4 with the JP8 had already been shunted. It seems like this port is working with the board that labeled 6xx-4133R-0D, but failed with 6xx-4133R-0B. This label can be viewed on the bottom of the board. The sticker of 6xx-4133R-0D is covering the original board printing 6xx-4133R-0B, as 0D's board comes with the extra 10pin male header, while 0B's board doesn't and one must solder the pins by himself.  

I think this is a hardware bug. :mad:
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Valued Contributor III
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I only know the revision as documented in the design files available at altera.com. It has J4 as assembled part and the JTAG interface seems operational. Has the 0B revision also the bus buffer U10 placed at the right of J4?

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Valued Contributor III
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fyi... 

 

i have two boards and they are labeled: 6xx-41333r-0b. both are working fine using either the usb and byteblaster-ii. also, i purchased the hsmc to gpio from terasic and designed a daughter board to translate the signals to ttl level (total of 72 bidirectional digital io). 

 

>Has the 0B revision also the bus buffer U10 placed at the right of J4? 

yes.
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