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Altera_Forum
Honored Contributor I
1,687 Views

Cyclone III StarterKit EP3C25F324C6 DDR-Problem

Hi everyone,

 

i have a problem with a small example configuration of a Nios II System using DDR.

I use quartus 8.1 full license.

I get fitting errors which tell me the following:

-----------------------

Error: Can't place pin ddr_mem_dqs[1] to location T8

Error: Can't place VREF pin T6 (VREFGROUP_B3_N0) for pin ddr_mem_dqs[1] of type bi-directional with SSTL-2 Class II I/O standard at location T8.

Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin T6 (VREFGROUP_B3_N0) is used on device EP3C25F324C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads is allowed when voltage reference pins are driving in, but there are potentially 10 pins driving out.

-----------------------

This is the used pin assingment:

-----------------------

 

I was told by someone else, that this error occurs because of a pin that has been assigned twice. But i don't find any information about that!

Does anyone know how to solve this problem?

 

Best regards,

 

Frank

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10 Replies
Altera_Forum
Honored Contributor I
84 Views

Hi froeben, 

You must miss some assignments for ddr signals. Try to follow “Specify the Top-Level Design Pin Out” section of http://www.altera.com/literature/an/an517.pdf.
Altera_Forum
Honored Contributor I
84 Views

 

--- Quote Start ---  

Hi everyone, 

 

i have a problem with a small example configuration of a Nios II System using DDR. 

I use quartus 8.1 full license. 

I get fitting errors which tell me the following: 

----------------------- 

Error: Can't place pin ddr_mem_dqs[1] to location T8 

Error: Can't place VREF pin T6 (VREFGROUP_B3_N0) for pin ddr_mem_dqs[1] of type bi-directional with SSTL-2 Class II I/O standard at location T8. 

Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin T6 (VREFGROUP_B3_N0) is used on device EP3C25F324C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads is allowed when voltage reference pins are driving in, but there are potentially 10 pins driving out. 

----------------------- 

<snip> 

 

I was told by someone else, that this error occurs because of a pin that has been assigned twice. But i don't find any information about that! 

Does anyone know how to solve this problem? 

 

Best regards, 

 

Frank 

--- Quote End ---  

 

 

Frank, 

This can also occur when there are conflicting I/O Standards selected. 

In this case you have too many Output/BiDirectional pins on IOBANK 3. 

Mike
Altera_Forum
Honored Contributor I
84 Views

Dear Mike, 

 

i used a megafunction of quartus 8.2 for connecting the DDR-Ram and i used the documented pinout of the dev-kit. Since there is no pin assignment documented in the pqf files according T6, i'm a little bit confused about the error.  

 

So i don't know where the wrong pin assignement is done. I didn't do it.... 

Where and how can i search for the wrong pin which is not shown in the pin assignment editor? 

 

Best regards, 

Frank
Altera_Forum
Honored Contributor I
84 Views

I am also getting this fitter error for Dqs pin....any luck on how two remove it?

Altera_Forum
Honored Contributor I
84 Views

There is a TCL script included with the Cyclone III kit that when ran changes the constraints and allows the design to compile. 

 

 

Tools> TCL Scripts > ddr_pin_assignments.tcl > Run 

 

That will allow it to compile. Read the comments if you have changed 

any of the default names. 

 

This was found in the DDR high performance controller PDF.
Altera_Forum
Honored Contributor I
84 Views

If you still have problems another approach may be to open an example design that already uses the DDR (e.g. the nios example in the starter kit pack) and then modify it to your needs.

Altera_Forum
Honored Contributor I
84 Views

Thanks brentsinger, 

 

I have allready tried & modified in their refrence design as required, it worked. But i am getting some issues(fitter error) if i try to build the new system which SOPC.. 

 

i will try msnook sugession to fix fitter error
Altera_Forum
Honored Contributor I
84 Views

I have the exact same problem that froeben described and like him I don't understand why because it is the exact same pin assignment that is on the CIII Starter Kit. 

 

I tried this with no success: 

 

1. MSNOOK's suggestion: Tools> TCL Scripts > ddr_pin_assignments.tcl > Run 

[ I still get the same error described by froeben] 

 

2. BrentSinger's suggestion: This will for DDR but it will just created even tougher problems when trying to add in the previously working USB2 core from the first working example I was trying to work off. 

[It will be much easier if I could just get around this fitter error] 

 

Any other advice before I go digging into AN517, that EOFZ recommended? 

 

Cheers
Altera_Forum
Honored Contributor I
84 Views

TO_BE_DONE

Altera_Forum
Honored Contributor I
84 Views

I was struggling with the same issue, and finally can confirm that adding OUTPUT_ENABLE_GROUP constraint to combine all DDR_DQ/DDR_DM/DDR_DQS lines can fix it. 

Thanks to MAX232 for posting this solution.
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