I have the Cyclone IV GX Transceiver Starter Kit. I am trying to use the bts_general project included with it. For comparison's sake, I am compiling it with two different Quartus versions, 10.1 and 12.1. The two versions are installed on separate machines.In 10.1, the design compiles and fits in the Cyclone IV EP4CGX15BF14C6, using up 24% of total logic elements. The sopc system (bts_general_sopc_inst) uses 3399 Logic Cells, 2208 Dedicated Logic Registers. In 12.1, the design won't fit. "Error (170012): Fitter requires 971 LABs to implement the project, but the device contains only 900 LABs". Here, the sopc system uses 10471 Dedicated Logic Registers. The fitter doesn't get to the point where it starts assigning Logic Cells. That's a pretty big change, going from 24% utilization to well over 100%. Has anyone compiled bts_general with a post-10.1 version? One obvious difference between the two is that 10.1 still has SOPC Builder, where 12.1 make you use Qsys. The project comes with a .sopc file, which Qsys converts. Is something going on there? Is Qsys just naturally that much of a pig?
I guess some device in your sopc uses some memory (1kB, according to DLR usage difference) which 10.1 implemented with block RAM, while 12.1 now synthesizes with logic cell registers. Probably Qsys and SOPC builder optimiize the design in different ways.Check device options in Qsys: for some of them you can explicitly select to use registers rather than block RAM. You can also browse Quartus Fitter report in order to show resource utilization for each design entity.