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Valued Contributor III
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Cyclone IV GX Dev Kit - Errata / Faults / Problems

Cyclone IV GX Dev Kit - Errata / Faults / Problems 

dk-dev-4cgx150n 

 

I'm just going to post stuff here as I find it so that other people have a chance of finding it when they hit similar problems. 

 

I'm afraid I've given up creating problem reports with Altera as they just get ignored which is no help to other people when they hit the same issue. Altera, if you actually read this, please put an Errata document with this info on the dev kit page. It makes you look worse not having it than it does publishing this information.
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Valued Contributor III
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LCD design fault. If you can't get the LCD working - see here: http://www.alteraforum.com/forum/showthread.php?t=42756

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Valued Contributor III
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Max II code fault. If you are having problems getting the board to power up into user space and then staying there - see here: http://www.alteraforum.com/forum/showthread.php?t=42755

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Valued Contributor III
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Schematic fault. 

 

Rev 01 of the schematic has the direction of the following pins wrong on sheet 15. 

ENET_T_RX_CLK is an output from the 88E1111 rather than an input as shown on the sheet port connector. 

ENET_MDC is an input to the 88E1111 rather than an output as shown on the sheet port connector. 

ENET_INTn is an output from the 88E1111 rather than an input as shown on the sheet port connector.
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Valued Contributor III
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The dev kit uses a Marvell 88E1111 PHY for the Ethernet but getting it working in your own design is really rather difficult (and I haven't got it working yet....) 

 

The PHY chip is has a data sheet which is hidden behind an NDA. This makes it rather difficult to work out what you need to do to get it working. 

 

The schematic states that the default setting is RGMII. However, this support doc says that it is SGMII http://www.altera.co.uk/support/kdb/solutions/rd12262011_851.html 

 

Which is correct? Who knows, as I can't get hold of a copy of the Marvell data sheet. 

 

To implement the fix requires knowledge of the address of the PHY chip. Fortunately, Dave WH has found this out: 

 

 

CONFIG[0] = LED_RX = 010b => PHY address [2:0] = 010b 

CONFIG[1] = LED_LINK10 = 110b => PHY address [4:3] = 10b 

 

So PHY address [4:0] = 10010b = 12h 

 

From: http://www.alteraforum.com/forum/archive/index.php/t-39638.html 

 

Thanks Dave WH 

 

 

More on my progress with this problem here: http://www.alteraforum.com/forum/showthread.php?t=44206
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Valued Contributor III
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Schematic Fault 

 

First pages shows 32MB of DDR2 connected to the top bank and 32MB of DDR2 connected to the bottom bank. i.e. 64MB total on the board. 

 

The correct figures are 64MB top and 64MB bottom making a total of 128MB on the board. This is made up of 4 x MT47H16M16 = 4 x 16Mb x 16 = 1024Mb = 128MB. 

 

I guess we don't complain about this :-)
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