Cyclone IV GX Transceiver Starter Kit for PCIe by SOPC

[Altera_Forum]

I got Cyclone IV GX Transceiver Starter Kit. Using SOPC Design example from PCIe user guide, I compiled the example. I assigned pins for PCIe tx, rx, and refclock since the example doesn't talk about it. As for the other signals, I assigned them to be all virtual.  

 Here are the signal names: cal_clk, clk_0, pcie_rstn_pcie_compiler_0, refclk_pcie_compiler_0, rx_in0_pcie_compiler_0, and tx_out0_pcie_compiler.   PC doesn't see Cyclone IV GX during enumeration. I'm wondering if I'm missing any other settings from SOPC since the example is generic. Anyone tried to target Cyclone IV GX Transceiver starter kit using SOPC design example?  Thanks in advance.

[Altera_Forum]

--- Quote Start ---   Here are the signal names: cal_clk, clk_0, pcie_rstn_pcie_compiler_0, refclk_pcie_compiler_0, rx_in0_pcie_compiler_0, and tx_out0_pcie_compiler.    --- Quote End ---  I'd be pretty concerned about not connecting signals called clock.  I would recommend creating a Modelsim simulation for your design.  Altera has been sending out emails regarding a PCIe webinar lately. I have not watched it, but it might have something interesting in it  http://www.altera.com/education/webcasts/all/source-files/wc-2011-pcie-technology-design-fpga/player.html  Cheers, Dave

[Altera_Forum]

Testbench which was generated from SOPC does work. Apparently, SOPC flow example is not really simple. I'm sure I'm repeating someone's footsteps.  

 This is from mySupport regarding SOPC flow.  -------------------------------------------------------------------------- 1. Generate free running 50MHz reconfig_clk and 125MHz fixedclk. They both should NOT be derived from 100MHz refclk or its derived clocks.  PCIe UG Figure 7-1 shows these clocks connection, it uses a free running 100MHz and derive fixedclk & reconfig_clk through GPLL.  http://www.altera.com/literature/ug/ug_pci_express.pdf?#page=178  2. Created the reconfig_blk and before compiling Quartus II design, regenerate the reconfig_blk  with input offset_cancellation_reset port. The reconfig block is needed for transceiver offset cancellation.  To generate this port, run the following command   (using Windows command prompt and cd to project reconfig.v file location):  qmegawiz -silent -wiz_override="offset_cancellation_reset" <altgx_reconfig filename.v>   Kindly refer below solution for more details on reconfig_clk and offset_cancellation_reset connection.  http://www.altera.com/support/kdb/solutions/rd12172009_309.html  3. Keep reconfig block in reset (assert offset_cancellation_reset input) until both reconfig_clk and fixedclk are stabled.  For example, if both of this clocks are derived from the same PLL, then offset_cancellation_reset = !(pll_locked)  In other words, the offset_cancellation_reset is the invertion of "pll_locked" (a NOT Gate in between).   See Figure 7–1. 'Internal Reset Modules in the Hard IP Implementation' of the PCIe User Guide for the illustration.   4. Connect the busy signal of reconfig block to the busy_altgxb_reconfig input of the PCIe block. --------------------------------------------------------------------------  I need to try this out. Not sure to generate reconfig_clk and fixedclk in SOPC or seperate module.

[Altera_Forum]

In the transceiver tests I have been doing with the Stratix IV GX kit (not PCIe related), reconfig_clk and cal_blk_clk can simply be connected to the 50MHz global clock (which connects to an external oscillator). If the Cyclone IV kit has a global clock pin connected to a 50MHz oscillator, then you can probably use that clock directly. 

 Cheers, Dave

[Altera_Forum]

If you can move to Q11, there is an example of the Qsys PCIe design for the C4GX starter. 

 http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs