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Valued Contributor III
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Cyclone IV GX dev kit HSMC connection buned MAXII BGA chip

Hi all, 

 

I have a serious question here. Please spend some time to read through my explanation below as I really need some help! I appreciate your time very much. 

 

Previously I used the Cyclone III starter board, with its HSMC connected to a self-designed extension board for my own application. The HSMC connection is treated as expansion IO for me to pass data to and from between the Cyclone III started board and my own extension application board. My FPGA program is functioning well. 

 

Then I decided to migrate to Cyclone IV GX development kit. The same extension board of my own is used. The HSMC connection was made to the HSMC A of C4GX as I know HSMC B is sharing with PCIe. So I use the HSMC A port to be at the safe side. 

 

Before I powered on the C4GX, I plugged the HSMC A connection to my extension board properly. Then, once I powered on C4GX through the PCIe 12V, in just 1-2seconds time, smoke came out from the MAXII EPM2210GF256C3N CPLD and I quickly powered off. The MAXII is burned! I am confused as I do not understand why this happened.  

 

I have a few things to make clear: 

1) My own extension board is fully functional without any short circuit and it is waiting for voltage supply from HSMC. Before and after the incident, I tested my extension board on C3starter kit and it is still fully functional. 

2) I have not yet programmed the C4GX. Once it is powered on, it will load the factory programmed code inside flash memory. Is this the culprit? But I have checked the C:\altera\11.0\kits\cycloneIVGX_4cgx150_fpga\examples\board_update_portal program code that is supposed to be the factory pre-program code, it seems that it doesnt do any pin assignment to the HSMC A port. So I suppose it is not causing the problem. 

3) I am not sure whether the C4GX FPGA is damaged or not because i cant test it. But for sure is I saw smoke from MAXII and its package case is slightly cracked. 

4) I am sure that the PCIE connection for voltage supply is correct because before this I did use the C4GX dev kit to run some other PCIe ref design and as well as other programs. All this while I use the PCIe connection to power up the C4GX dev kit during development.  

5) I have checked the reference manual of C4GX dev kit and it seems that MAXII does not have direct connection to HSMC A. Correct me if I am wrong. So I cant understand why the MAX II burned. 

 

So, please, anyone can provide me with some help/advices. I appreciate very much. I really need to find out the reason of why this occured. 

 

thank you.
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Valued Contributor III
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HI, according to the Cyclone IV GX reference manual (p.38 under HSMC subtitle), it says "The HSMC port A interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible." 

 

With that, is 3.3V permitted as input signal for HSMC Port A? 

Or only max up to 2.5V is accepted? 

If I supply 3.3V as input signal voltage to HSMC Port A, is there the possibility that it causes the MAXII to burn?
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Valued Contributor III
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--- Quote Start ---  

HI, according to the Cyclone IV GX reference manual (p.38 under HSMC subtitle), it says "The HSMC port A interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible." 

 

With that, is 3.3V permitted as input signal for HSMC Port A? 

Or only max up to 2.5V is accepted? 

If I supply 3.3V as input signal voltage to HSMC Port A, is there the possibility that it causes the MAXII to burn? 

--- Quote End ---  

 

 

I'm not sure about the CIV board but the CIII started board has 2.5V IO with no protection on the inputs so I'd wouldn't expect the inputs to reliably work / survive with 3.3V. 

 

If the Max device can see the HSMC pins it might be that it's got 2.5V IO and can't withstand 3.3V. 

 

 

Nial.
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Valued Contributor III
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--- Quote Start ---  

I'm not sure about the CIV board but the CIII started board has 2.5V IO with no protection on the inputs so I'd wouldn't expect the inputs to reliably work / survive with 3.3V. 

 

If the Max device can see the HSMC pins it might be that it's got 2.5V IO and can't withstand 3.3V. 

 

 

Nial. 

--- Quote End ---  

 

 

Last time before I used CIVGX board, I tested and run the same design on CIII Starter board too. Through the HSMC, I give 3.3V input signal and it is still functioning well. So I have no idea why it is not functioning in CIVGX. 

 

Also, I find the MAXII device does not connect to HSMC pins. Attached the MAXII block diagram from the C4GX reference manual. 

 

Pls advice if I understand the block diagram wrongly. 

Thank you.
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Valued Contributor III
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This is probably not an explanation why the MAX II smoked, but I just want to point out one thing: 

 

By default the C4GX Dev Kit is configured to use 1.8V as the I/O voltage for banks 5 & 6. And many of the HSMC pins are connected to banks 5 & 6 ... 

 

In order to change to IO voltage 2.5V for those banks, you should shunt the jumper J3. See the table 2-45 in the G4GX DevKit reference manual. 

 

We were lucky and our board survived but without this jumper our HSMC board did not work correctly ... 

 

Regards, 

Jari
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Valued Contributor III
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The most plausible explanation for getting "smoke" on the daughter board is that you inadvertently connected to a 12V-pin of the HSMC connector. You should check all pins in the vicinity of the 12V node for possible shorts.

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Valued Contributor III
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--- Quote Start ---  

This is probably not an explanation why the MAX II smoked, but I just want to point out one thing: 

 

By default the C4GX Dev Kit is configured to use 1.8V as the I/O voltage for banks 5 & 6. And many of the HSMC pins are connected to banks 5 & 6 ... 

 

In order to change to IO voltage 2.5V for those banks, you should shunt the jumper J3. See the table 2-45 in the G4GX DevKit reference manual. 

 

We were lucky and our board survived but without this jumper our HSMC board did not work correctly ... 

 

Regards, 

Jari 

--- Quote End ---  

 

 

Shunt the jumper J3 means to connect it? 

I thought to make it to 2.5V IO is to assign at pin planner so that it is 2.5V LVCMOS? Because it seems that shunt the jumper J3 is for power management kind of stuff? 

and, you mentioned without the jumper your HSMC board did not work correctly. The HSMC board you mean is the host Altera board or the daughter card you connecting to? However, you didnt burn the board even though you give it 2.5V while it is configured for 1.8V right? 

 

Well, I still have no progress on my finding. Because it still seems to me that there is no direct connection between HSMC and MAX II. So no matter HSMC is supporting 1.8V, 2.5V or 3.3V, it still seems to me to not possible to damage the MAXII CPLD.
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Valued Contributor III
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Yes, with "shunt" I mean connecting it. 

 

With Pin planner you can configure the FPGA to use a certain I/O standard internally, but J3 selects the actual I/O voltage (VCCIO) given to the banks 5 and 6. Check the schematics ... 

 

Our HSMC daughter board and C4GX DevKit host board survived. The problem was found when an output signal from C4GX to HSMC daughter board was unoperational and was examined. It could be that we didn't have any 2.5V lines fed into C4GX's 1.8V I/O pins at that moment ... 

 

As FvM mentioned, 12V could cause "smoking" more likely than 1.8V vs. 2.5V difference. 

 

Note that there actually is a direct connection between HSMC and MAX II: HSMA_PSNTn and HSMB_PSNTn. Have you checked those lines ... 

 

Jari 

 

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Valued Contributor III
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--- Quote Start ---  

Last time before I used CIVGX board, I tested and run the same design on CIII Starter board too. Through the HSMC, I give 3.3V input signal and it is still functioning well. So I have no idea why it is not functioning in CIVGX. 

--- Quote End ---  

 

 

Sorry to be blunt but I don't care what you escaped without destroying before you broke the CIVGX. 

 

The Cyclone IV data sheet in I/O Stardard Specifications, Table 1-15 in the version I have, says VinHigh Max for a 2.5V IO is Vcc+0.3V, ie 2.8V. 

 

If you're driving anything higher in you're asking for trouble (unless you add properly calculated current limiting resistors). 

 

 

--- Quote Start ---  

 

Also, I find the MAXII device does not connect to HSMC pins. Attached the MAXII block diagram from the C4GX reference manual. 

Pls advice if I understand the block diagram wrongly. 

Thank you. 

--- Quote End ---  

There isn't enough detail in that to diagnose the problem, try to get hold of the schematics and trace all the HSMC connections. 

 

 

Nial
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Valued Contributor III
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--- Quote Start ---  

The most plausible explanation for getting "smoke" on the daughter board is that you inadvertently connected to a 12V-pin of the HSMC connector. You should check all pins in the vicinity of the 12V node for possible shorts. 

--- Quote End ---  

 

 

Smoke is seen on the host board MAXII CPLD, not daughter board.  

The host board is the Cyclone IV GX dev kit. 

I have triple checked the 12V and GND pins. They are not shorted and are matched on the correct pins.
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Valued Contributor III
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--- Quote Start ---  

Yes, with "shunt" I mean connecting it. 

 

With Pin planner you can configure the FPGA to use a certain I/O standard internally, but J3 selects the actual I/O voltage (VCCIO) given to the banks 5 and 6. Check the schematics ... 

 

Our HSMC daughter board and C4GX DevKit host board survived. The problem was found when an output signal from C4GX to HSMC daughter board was unoperational and was examined. It could be that we didn't have any 2.5V lines fed into C4GX's 1.8V I/O pins at that moment ... 

 

As FvM mentioned, 12V could cause "smoking" more likely than 1.8V vs. 2.5V difference. 

 

Note that there actually is a direct connection between HSMC and MAX II: HSMA_PSNTn and HSMB_PSNTn. Have you checked those lines ... 

 

Jari 

 

 

--- Quote End ---  

 

 

thanks for reminding. I didnt really put my attention on HSMA_PSNTn signal before this. I was keep on focusing on the IO signal. 

 

Currently checking the schematic for HSMA_PSNTn. However, I dont really understand how is the connnection should be. In the C4GX dev kit schematic, it shows that HSMA_PSNTn signal from the HSMC connector interface is connecting to MAXII (pin G5), C4GX (pin A25), and also connecting from 3.3V with green LED (D1) and resistor (R1). 

 

Thus, may you advice how your daughter card connecting this HSMA_PSNTn pin? Did you connect it to GND at daughter card or supply what voltage signal? 

Mind to explain how does this HSMA_PSNTn signal functions? because I dont understand its flow. 

 

 

 

--- Quote Start ---  

Sorry to be blunt but I don't care what you escaped without destroying before you broke the CIVGX. 

 

The Cyclone IV data sheet in I/O Stardard Specifications, Table 1-15 in the version I have, says VinHigh Max for a 2.5V IO is Vcc+0.3V, ie 2.8V. 

 

If you're driving anything higher in you're asking for trouble (unless you add properly calculated current limiting resistors). 

 

There isn't enough detail in that to diagnose the problem, try to get hold of the schematics and trace all the HSMC connections. 

 

 

Nial 

--- Quote End ---  

 

 

Thank you. 

As you advice, I am trying to troubleshoot from the schematics to trace the HSMC connections right now. 

But I dont understand how the HSMA_PSNTn signal is being drive. It is driven by 3.3V and it is also connecting to MAXII and FPGA and to the daughter card. So at my daughter card, should I drive the HSMA_PSNTn pin to GND or supply it with what voltage value? 

 

Advice are very much appreciated.
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Valued Contributor III
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From the C4GX DevKit Reference Manual, table 2-8 Board-Specific LEDs: "D1 PSNTN A  

Green LED. Illuminates when the HSMC port A has a board or cable 

plugged-in such that pin 160 becomes grounded. Driven by the add-in 

card." 

 

So your daughter board should connect the PSNTn pin directly to the GND. 

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Valued Contributor III
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--- Quote Start ---  

From the C4GX DevKit Reference Manual, table 2-8 Board-Specific LEDs: "D1 PSNTN A  

Green LED. Illuminates when the HSMC port A has a board or cable 

plugged-in such that pin 160 becomes grounded. Driven by the add-in 

card." 

 

So your daughter board should connect the PSNTn pin directly to the GND. 

 

--- Quote End ---  

 

 

I see.. I appreciate very much. 

I think this might be one of the possible reason of why the MAXII burned. 

Because at the daughter card, I am actually supplying voltage to the HSMA_PSNTn line into C4GX dev kit. 

 

However, since this HSMA_PSTNn also connecting to C4GX FPGA, I affraid the FPGA might have already burned as well. I need to check on that. 

 

By the way, what is the function of EPCS128 used for? 

Because I detected that my voltage supply of 3.3V from LTC3850 is shorted and I identified that EPCS uses 3.3V supply. I affraid this IC is damaged too. May I know what's the function of this IC? 

 

thank you. 

 

 

Thank you again.
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Valued Contributor III
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Hi all, 

 

for C4GX dev kit HSMC port A, pin 96 (HSMA_CLK_IN_P1), 98 (HSMA_CLK_IN_N1), 156 (HSMA_CLK_PIN_P2), 158 (HSMA_CLK_IN_N2), I would like to use these 4 pins as output.  

 

In c4gx reference manual, pg40, Table 2-32, it describes these pins as e.g. LVDS or CMOS clock in 1 or CMOS bit 37.  

 

How or what configuration I need in order to use these clocks input pins as normal general purpose output pin? 

 

thank you
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Valued Contributor III
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--- Quote Start ---  

Hi all, 

for C4GX dev kit HSMC port A, pin 96 (HSMA_CLK_IN_P1), 98 (HSMA_CLK_IN_N1), 156 (HSMA_CLK_PIN_P2), 158 (HSMA_CLK_IN_N2), I would like to use these 4 pins as output.  

 

In c4gx reference manual, pg40, Table 2-32, it describes these pins as e.g. LVDS or CMOS clock in 1 or CMOS bit 37.  

 

How or what configuration I need in order to use these clocks input pins as normal general purpose output pin? 

thank you 

--- Quote End ---  

 

 

As before, you need to get the schematics for the C4GX reference board, they have all the information you need. 

 

Find out which FPGA pins those HSMC nets are connected to and if you can, assign them as outputs. 

 

[Edit] I see you have the schematics. Create a series of outputs and assign them to the pins those nets are connected to. If Quartus allows the pin assignment in the FPGA build then you're done. [/Edit] 

 

 

 

Nial
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