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Altera_Forum
Honored Contributor I
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Cyclone IV GX starter Kit - PCIe

Hi, 

 

I am trying to test the PCIe on the Cyclone IV GX starter kit, I am using the standard chaining DMA example. I have configured the PCIe as Endpoint with x1. I am able to see the Device in the PCItree software which i am running in the PC.  

Can anyone clarify me about the BAR registers configured. I tried with 32bit non prefetchable bars for BAR0 and BAR1. i am able to see the configuration in the PCITREE, but when i try to access the bar1 memory, it shows it same as bar0 memory.  

the st_bar_dec0 increments when i access the bar0 and bar1. 

My main requirement is to map two seperate logic to two different bars to the PCIe. 

I have also observed in the <instance_name_core>.vhd file, in the component "altpcie_hip_pipen1b" the generic mapping for the core for pcie_mode="SHARED_MODE", whose details i could not find in the IP compiler guide. 

 

Can anyone help me to resolve this issue? 

 

Thanks in advance, 

Shubha
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Altera_Forum
Honored Contributor I
50 Views

Before guiding you through the proper decoding of the BAR indication for received packets, I would question that you need two different BARs of equal kind for your different function’s tasks. Just split your BAR address range, say, the address range from 0x0000 to 0x0FFF is used for your first logic, then from 0x1000 to 0x1FFF for your second logic. You just have to decode the appropriate address wire. And your driver won’t mind either.

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