Hi there,
Taking example for typical bootflow. For Arria 10 SoC, there is a feature called Early IO Release mode, when this is enabled you may configure part of the FPGA bit-stream (peripherals, DDR, I/Os .etc) which will improve the boot up time significantly from a typical bootflow.
Cyclone V does not have this feature, but you may boot the HPS and FPGA separately, whether the HPS first or FPGA first depending on your design. Based on my experience, configuring the FPGA first might be a bit complex.
I recommend that you read our Booting User Guide here, its super useful. Please do not forget to bookmark/save them as future reference:
Cyclone V SoC:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an709.pdf
Arria 10 SoC:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-a10-soc-boot.pdf
Arria 10 SoC Early IO Rlease:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-fpga-early-io-release.pdf
Additional referrence:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-guidance/soc-bootloader.html
My apology for the late response due to Lunar New Year.
Regards.
