We have a custom FPGA board with the Cyclone V GT device. Part number 5CGTFD9EF35.
There is a rare issue that occurs where the device periodically goes through the init and config cycles potentially delaying the boot up time by a significant margin. The "INIT_DONE" and "CONF_DONE" signals from the Altera are toggling while this is happening. The init/config process restarts very rapidly, multiple times a second. This lasts for several seconds. The init/config completes and stabilizes (the board appears to successfully come up and load its firmware) for a couple seconds and this cycle repeats itself indefinitely.
When it Happens:
The issue is rarely seen from a cold boot, but can be reliably reproduced if the board is power cycled after running for about 45 mins+.
During the period where the init/config process is compromised and cycling, we have determined none of the voltages on the board go through any kind of drop. We have also determined that the reset signal going to the altera is not being toggled during this time.
What causes the init/config process to lose integrity and start over?
What can we measure to give more insight into the problem?
How can this issue be remedied on future boards?
The problems you had mentioned can occur due to improper terminations on the board.
Please check if the board connections are as per the Cyclone V Pin Connection Guildelines: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
Also check recommendations in the following Knowledge base:
Please let us know your observations.
We found several instances of incorrect termination of the related pins in the document you linked to. After correcting these, the severity of the issue may have been marginally reduced but it is not eliminated completely.
We have been trying different configuration settings and different configuration devices with no luck. The longer the board is powered, the worse this issue gets. Not only does the issue happen more frequently over time, but the amount of time it spends trying to configure increases as well.
The duration of the time spent trying to config is also very random. Ranging from 1 to 40 seconds.
Do you happen to have any more insights or data points we could get?
Did you monitor the nSTATUS and nCONFIG pins? In some cases, if these pins are unexpectedly driven by an external monitoring device, then repeated cycles may be triggered. Please make sure that the pins are connected through proper pull-up resistor value mentioned in the connection guideline.
You can also take help of the Cofiguration troubleshooter: FPGA Configuration Troubleshooter (intel.com)
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