I am trying to compile top project containing NIOS + my design (let's call it abc) on Cyclone V GT development kit. My design is tight on resources. It supports 1220 M10K blocks and 1770 Kb of MLABs.
In my design abc, there is a submodule MAC, submodule divider (which uses lpm_divide IP) which i have instantiated 13 times. When I compile just the design abc, only the 13th instance is showing different
here is what the memory usage looks like entity wise:
MAC submodule - 0 M10K blocks (there is no logic that instantiates M10k or mlab)
DIVIDER submodule - 6 M10K blocks
But when I try adding Nios with abc and compile, here is the fitter report:
MAC: - 17 M10K blocks, 480 MLABs.
DIVIDER: 0 M10K (but uses 8 mlabs instead)
Due to extra 11 (17 - 6) M10K blocks my fitter is failing sometimes, sometimes it passes.
The fitter report shows MLABs usage to be 932.
1) I am not understanding whether this is number of MLABs cells or blocks. OR how to calculate number of total MLABs present in the FPGA. How to calculate it?
2) Why is my submodule MAC using 17 M10ks when I have not instantiated any bram for M10k or MLAB? What can I do to solve this issue?