FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5410 Discussions

Cyclone V HPS - Maximum frequency only 200 BogoMIPS

vrbavojtech
Novice
299 Views

Hello,

I am trying to figure out why in /proc/cpuinfo I have only 200 BogoMIPS as the maximum CPU frequency:

processor       : 0
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 200.00
Features        : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

processor       : 1
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 200.00
Features        : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

Hardware        : Altera SOCFPGA
Revision        : 0000
Serial          : 0000000000000000

The content of /sys/kernel/debug/clk/clk_summary is:

                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 osc1                                 5        5        0    25000000          0     0  50000         Y
    sdram_pll                         0        0        0   800000000          0     0  50000         Y
       h2f_usr2_clk                   0        0        0   133333333          0     0  50000         Y
          h2f_user2_clk               0        0        0   133333333          0     0  50000         ?
       ddr_dq_clk                     0        0        0   400000000          0     0  50000         Y
          ddr_dq_clk_gate             0        0        0   400000000          0     0  50000         ?
       ddr_2x_dqs_clk                 0        0        0   800000000          0     0  50000         Y
          ddr_2x_dqs_clk_gate         0        0        0   800000000          0     0  50000         ?
       ddr_dqs_clk                    0        0        0   400000000          0     0  50000         Y
          ddr_dqs_clk_gate            0        0        0   400000000          0     0  50000         ?
    periph_pll                        3        3        0  1000000000          0     0  50000         Y
       h2f_usr1_clk                   0        0        0    50000000          0     0  50000         Y
          h2f_user1_clk               0        0        0    50000000          0     0  50000         ?
       per_base_clk                   3        3        0   200000000          0     0  50000         Y
          gpio_db_clk                 0        0        0       32000          0     0  50000         ?
          can1_clk                    0        0        0    40000000          0     0  50000         ?
          can0_clk                    0        0        0    40000000          0     0  50000         ?
          spi_m_clk                   0        0        0   200000000          0     0  50000         ?
          usb_mp_clk                  1        1        0   200000000          0     0  50000         ?
          l4_sp_clk                   3        3        0   100000000          0     0  50000         ?
          l4_mp_clk                   1        1        0   100000000          0     0  50000         ?
       per_nand_mmc_clk               1        1        0   200000000          0     0  50000         Y
          nand_x_clk                  0        0        0   200000000          0     0  50000         ?
             nand_clk                 0        0        0    50000000          0     0  50000         ?
             nand_ecc_clk             0        0        0   200000000          0     0  50000         ?
          sdmmc_clk                   1        1        0   200000000          0     0  50000         ?
             sdmmc_clk_divided        1        1        0    50000000          0     0  50000         ?
       per_qsi_clk                    0        0        0     1953125          0     0  50000         Y
       emac1_clk                      1        1        0   250000000          0     0  50000         Y
          emac_1_clk                  1        1        0   250000000          0     0  50000         ?
       emac0_clk                      0        0        0     1953125          0     0  50000         Y
          emac_0_clk                  0        0        0     1953125          0     0  50000         ?
    dbg_base_clk                      0        0        0     6250000          0     0  50000         Y
       dbg_timer_clk                  0        0        0     6250000          0     0  50000         ?
       dbg_trace_clk                  0        0        0     6250000          0     0  50000         ?
       dbg_at_clk                     0        0        0     6250000          0     0  50000         ?
          dbg_clk                     0        0        0     3125000          0     0  50000         ?
    main_pll                          2        2        0  1600000000          0     0  50000         Y
       cfg_h2f_usr0_clk               0        0        0   100000000          0     0  50000         Y
          h2f_user0_clk               0        0        0   100000000          0     0  50000         ?
          cfg_clk                     0        0        0   100000000          0     0  50000         ?
       main_nand_sdmmc_clk            0        0        0     3125000          0     0  50000         Y
       main_qspi_clk                  0        0        0     3125000          0     0  50000         Y
          qspi_clk                    0        0        0     3125000          0     0  50000         ?
       mainclk                        1        1        0   400000000          0     0  50000         Y
          l3_mp_clk                   0        0        0   200000000          0     0  50000         ?
             l3_sp_clk                0        0        0   100000000          0     0  50000         Y
          l3_main_clk                 0        0        0   400000000          0     0  50000         Y
          l4_main_clk                 3        4        0   400000000          0     0  50000         ?
       mpuclk                         1        1        0   800000000          0     0  50000         Y
          mpu_l2_ram_clk              0        0        0   400000000          0     0  50000         Y
          mpu_periph_clk              1        1        0   200000000          0     0  50000         Y

I am using the latest altera-opensource/linux-socfpga kernel v5.19.

Somebody probably solved it in an another post, only stating that they had to change clocks/PLL section in some DTS file based on some information from version 4.14.x of the kernel in the github repository, but didn’t provide any detail and I am struggling to find the information there.

Does anybody know what changes must be made to get 1594.16 BogoMIPS (as shown in the forum post)?

Also, based on the HPS Technical Reference Manual, both cores should have 2.5 MIPS per MHz, so I would expect 2000 BogoMIPS at 800MHz mpuclk, is that right?

Thanks for any help.

0 Kudos
5 Replies
JingyangTeh
Employee
241 Views

Hi


The value from the CycloneV TRM is using another benchmark standard.

That could be the reason in the difference in value.

In my knowledge Intel did not provide any official MIPS benchmarking on the CycloneV boards.


The changes made in the dts could be overclocking the MPU which could result in the higer BogoMIPS.


REgards

Jingyang, Teh


vrbavojtech
Novice
231 Views
Hello,
thank you for the answer.

I probably need some clarification of the BogoMIPS value and its meaning. I don't know about any reliable method for measuring real MIPS of the cores.
Does that mean the HPS already achieves the best performance possible? Can anybody provide benchmark results for the best performance settings?
JingyangTeh
Employee
193 Views

Hi


BogoMips is a crude linux measurement of the processor performance. (https://en.wikipedia.org/wiki/BogoMips)


There is no official benchmark released by Intel on its FPGA SOC Boards.

However with the GSRD the boards are optimized between performance and power consumption.


Regards

Jingyang, Teh



JingyangTeh
Employee
138 Views

Hi


Happy New Year!

Any update on this case?


Regards

Jingyang, Teh


JingyangTeh
Employee
86 Views

Hi


Since a solution have been provided and no feedback was received, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


Reply