Hi,
I meet JTAG error while downloading the .sof file to the FPGA via "Programmer". It says that the JTAG Id isn't what the Programmer was expecting for. I use Cyclone V devloppement kit and Quartus II v.13 (64-bit). What can I do to avoid it ? (Screenshots are attached to this post). Thanks, https://www.alteraforum.com/forum/attachment.php?attachmentid=7650 https://www.alteraforum.com/forum/attachment.php?attachmentid=7651Link Copied
I have the same problome.
Please help!I am seeing a similar problem with the Cyclone V GT demo board, annoyingly on the GT demo board you have to have the MAX V CPLD system controller in the JTAG chain with the FPGA which is not like the GX demo board.
When I scan the JTAG chain it automatically detects the FPGA and CPLD correctly but when I try and load a sof in the FPGA and bypass the CPLD it fails. Does anyone know how to resolve this one?Hi guys,
Actually, my former problem is solved. JTAG ID Error occured because of unconstrained in/out of my design. To avoid it, make sure that all your in/out have a pin_location assigned. regards,Hi Basstudio,
Does your programmation start a few or not at all ? If yes, at how many percentage does the fail appear ?Thanks arriacinq but this is fine in my design.
The QuartusII programmer gets to 95% and then reports: --- Quote Start --- Error (209040): Can't access JTAG chain Error (209015): Can't configure device. Expected JTAG ID code 0x02B040DD for device 1, but found JTAG ID code 0x00000000. Error (209012): Operation failed --- Quote End --- Interestingly if I connect an old USB Byte Blaster to the JTAG header on the demo board (this automatically disables the embedded USB-Blaster-II) it works :confused:The USB-Blaster II on the Cyclone V board runs at 16MHz by default (unless you have a very old board in which case its default speed is set to 24MHz).
Does turning the speed down to 6MHz with the command below make things more reliable? jtagconfig --setparam <cable id> JtagClock 6M You can use --getparam to read the current speed.Interestingly I have got a what I think is a new Cyclone V GT development board because it has the updated silicon and it reported a JTAG speed of 24MHz.
I have now issued the config --setparam to 16MHz and see if that makes a difference, oddly it does work but not reliably - SignalTap usually causes it to go wrong.For more complete information about compiler optimizations, see our Optimization Notice.