Cyclone V Jtag programming Failed

[alberto_p]

Dear all,

I am a newbie here, so excuse me if I am in the wrong place to ask.

I have the following problem:

I have a custom made board with a Cyclone V FPGA (5CGX). I have 3 usb blasters Terasic (apparently the same model). With two of them I cannot program the board via Jtag; with the last one I can program the board. I see this problem with several custom made boards (same board model). If I try the "no-working" blasters on a different custom board model, it works. I think to have something "border-line" on my board but I cannot understand what it's going on.

Thanks for your help.

Details:

1) the jtag part is biased at 2.5V and it is going to the 3A bank, biased at 2.5V.

2) the MSEL part is biased at 3.3V and the pullup on the CONF_DONE, nCONFIG, nSTATUS and INIT_DONE are on 3.3V (my mistake, they should be at 2.5V event if on the Cyclone V device datasheet it is written that the max VIH for a bank at 2.5V is 3.6V...in principle it is not a good practice but it should work).

3) The FPGA is not always seen by the autodetect function of Quartus. If a try to program the FPGA with the .sof file, I do not see the percent bar working: it just shows "Failed" after a while and I see the message "CONF_DONE" pin is not set at 1 etc..etc.. If I open the Jtag Chain Debugger I can run the Jtag Chain test and I can run the IDCODE iteration for several cycles with no error (it seems that the FPGA is seen..)

4) I opened the case of the Terasic blaster and I checked the TCK,TDO,TMS and TDI signals with the oscilloscope: as far as I can see, the signals are arriving on the pcb board of the blaster and I can see them also before and after the voltage translator circuit (it means that the logic level should be ok): I did not check the whole duration of the .sof file but just a few transition at the beginning. I also checked the signals on my board and they seems to be ok. Also the timing seems to be good: the frequency of TCK is 6 MHz (as expected) and I have 40 ns of setup time.

[SreekumarR_G_Intel]

Hello there,

Interesting one ..quick thought ....Can you check with 6 MHz frequency? I believe by default it is 24 MHz.

Thank you,

Regards,

Sree

[alberto_p]

Hello,

thanks for the answer.

The frequency is 6 MHz... I searched around to change it but it seems to be the minimum frequency you can set.

In the meanwhile I tried again with the Jtag Chain Debugger and the IDCODE iteration test. It looks like, when I go up with iterations there is something wrong. I have a "Warning: Uncertain JTAG chain. Detected 1 device(s)". Not fully clear what it means but I am starting to think that, on a single iteration or with a few iterations, it works. As soon as I go high with iterations (which is also the case of a .sof file programming), there is something wrong with the bus. It is something that statistically happens: I cannot see it with a low number of iterations but when I go high it appears... Now, what exactly it is (TCLK, TDI, TDO...all of them..why it works with one bluster and not with the others....something else..)...no idea.

Regards.

[SreekumarR_G_Intel]

I am not really sure how I can help further from my side. If you have any specific question you can let me know ?

Thank you ,

Regards,

Sree