I am currently experimenting with a Cyclone V SoC (DE10-Nano-SoC Kit). Therefore, I implemented parts of the design with the help of QSys including Clock, HPS, PIO, SPI and JTAG UART, generated the HDL code and a .bsf file (block symbol file) and imported the files in qartus.
a) When setting the corresponding .qip-file (Qartus Prime IP file) as top-level entity, everything works fine.
b) When setting up a Block Diagram / Schematic file as top-level entity which includes the above-mentioned QSys-Design as block symbol, the fitter shows the following error.
Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 >
Error: Verify the following:
Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)
Error: The core is not the top-level of the project
Error: The memory interface pins are exported to the top-level of the project
What am I doing wrong? Please let me know, if further information is required.
Thanks and best regards
Is your project name same as bdf file name?
thanks for your prompt reply. Yes, the name of the project is identical to the .bdf-file name, but as mentioned above:
Thank you in advance.
We can to include .bsf in bdf file and set dbf as top level file. bsf file name should not be same as bdf.
Can you attach the project ?
Hi and thanks for your reply.
In the mean time, I found the solution for my problem. I did export "memory" and "hps_io" within qsys, but I did not connect any ports to it in quartus. After correcting this, the compilation runs perfectly. Furthermore, I switched from the block symbol design to textual design, even if it was not the root cause of my problem, but it feels more convenient.
However, thanks for your hep and best regards.