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Cyclone V SX SoC dev board - AHB

Honored Contributor II



I am using the Cyclone V SX SoC development kit and I need a connection to the ahb bus. At first I must connect an AHB slave and then an AHB master. I'm new to qsys. I have connected the h2f_axi master to an avalon mm master translator --> avalon mm master agent-->memory mapped router --> memory mapped traffic limiter --> AHB slave agent. Is this connection scheme the right one? (qsys interconnect Figure 9–5. Avalon-MM Master Network Interface) 


I have some errors in qsys: 

Error: System.merlin_router_0: Port src_channel is not fully defined after elaboration 

Error: System.merlin_master_agent_0.cp/merlin_router_0.sink: The source has 112 bits per symbol, while the sink has 8. 

Error: System.merlin_router_0.src/merlin_traffic_limiter_0.cmd_sink: The source has 8 bits per symbol, while the sink has 72. 

Error: System.merlin_traffic_limiter_0.cmd_src/merlin_ahb_slave_agent_0.cp: The source has 72 bits per symbol, while the sink has 118.Error: System.merlin_ahb_slave_agent_0.rp/merlin_traffic_limiter_0.rsp_sink: The source has 118 bits per symbol, while the sink has 72. 

Error: System.merlin_traffic_limiter_0.rsp_src/merlin_master_agent_0.rp: The source has 72 bits per symbol, while the sink has 112. 

Error: System.hps_0.h2f_axi_master: merlin_master_translator_0.avalon_anti_master_0 (0x0..0x3ffffffff) is outside the master's address range (0x0..0x3fffffff) 



Warning: System.merlin_router_0.src: Signal src_channel[-1] of type channel must have width [1-128] 

Warning: System.merlin_router_0.src: The channel signal isn't wide enough to support the number of channels. 




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