Are there any known issues that can cause the Cyclone V SOC to lockup on power up? We have a product where we are experience random boot failures in the field where the SOC appears to fail to boot. What I mean by this is if I probe the NOR flash pins where the bootloader is stored I see no activity at power on. The BSEL pins are properly tied high and appear to be stable at exit of POR.
We are powering the device up in the reverse order of what Intel recommends. However, the documentation just states the device may draw more power then expected at power on. The FPGA and SOC are basically powered on at the same time with the core for both powering up last.
Can you briefly explain on what was the step of the booting order that you used for testing?
Also, which document are you referring to? I may need to look it up.
- We have a Cyclone V SOC device, 5CSEBA5U23I7SN
- BSEL[2:0] = 111, The Boot Select pins are setup to boot from QSPI NOR and appear to be up and stable before POR. The HPS boots and then loads the FPGA.
- MSEL[4:0} value of 01010, Fast Power On
- We hold the HPS_nPOR signal low throughout the power up sequence and then an additional 100ms after the power up sequence. The clocks and power rails are stable by the point the HPS_nPOR signal is released.
- Documents I'm referencing are the Cyclone V Hard Processor System Technical Reference Manual, Cyclone V Device Handbook.
- Cyclone V Device Handbook indicates that you can power up the device in any order, and then gives you a table listing current transients at power on if you do not follow the recommended power up sequence.