Cyclone V TSE MAC timing closure

[Jodok]

I try to synthesize a tripple speed ethernet (TSE) MAC with rgmii on 5CGTFD9E5F31l7 and encounter timing missmatches.

The PHY is a DP83867IR and a TXV0106 level-shifter (+/- 0.3ns skew) is inbetween the FPGA and the PHY.

The MAC-IP is using the Rx-Clock as Tx-Clock (loopback), please see the top path in the *.png.

The Rx-Clock is red highlited on that diagram. The Tx-Clock is driven by a ddrio that itself is clocked by the Rx-Clock. The Tx-Data is driven by ddrio as well.

If you have a look on the timing report, you see that there is some negative slack for Tx setup and hold. This leads me to some questions I would like to discuss here:

1. Are the constrains provided reasonable?

2. Are there assignments to make to improve timing?

3. What could be improved on MAC side to meet timing?

4. Could switching to other ports (FPGA-Pins) improve timing?

5. Are there better suited FPGAs for this application?

Thank you in advnace.

[Jodok]

Any help on this would be greatly appreciated!

Jodok

[RichardTanSY_Intel]

Hi,

It's been a while since your last reply.

May I know if the issue has been resolved, or if you still need assistance with this case?

If so, could you kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi,

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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Richard Tan