Cyclone V Transceiver Design Missing

[JLee25]

Hi,

I follow the link to Cyclone V Transceiver PHY Design Example.

And the link to "Cyclone V Native PHY with manual alignment, 8b10b enabled and byte ordering in single width mode design example

".

Where can I get it?

Thank you.

Regards

Johnson

[CheePin_C_Intel]

Hi Johnson,

As I understand it, you are referring to one of the CV design example which was previously in wiki. For your information, the wiki is no longer accessible and this is why you are unable to download the design example. Please allow me some time to look into internal database to see if there is still back up of the design. I will update you by mid of the week. Please ping me if you do not hear back from me.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[JLee25]

Hi CheePin,

Any update on the design example?

Please let me know.

Thank you!

Best Regards,

Johnson Lee

[CheePin_C_Intel]

Hi Johnson,

Sorry for the delay and thanks for pinging me. I have just sent the ZIP file to your email because it seems like I am unable to attach to this case. Please let me know if you are not receiving it.

[JLee25]

Hi CheePin,

Thank you for the update.

I received the file.

Before I received this, I use Cv manual align byte order double width as a template.

But the simulation result looks like Word Aligner and Byte Ordering is not work.

I just change the settings of native phy.

I need your help to look at my settings and give me advice.

Should I open a new thread on this?

Regards,

Johnson

[JLee25]

Hi CheePin,

I ran the shared project and have questions need your help.

1. Why the "Byte Order Pattern" is 0x1BC, and it can work properly when the input pattern is BCEE ?
2. I change the TX signal from BCEE to BC60 and the Byte Order manual align still work?

My understanding about the Byte Ordering will arrange the output according to specified "Pattern".

But none of the above test pattern matched 1BC.

Do you think this result is correct?

BRs,

Johnson

[CheePin_C_Intel]

Hi,

Sorry for the delay. Frankly speaking, I am not sure why the Byte Order Pattern = 0x1BC in this example. My understanding is same as yours where we will need specific pattern ie 0xBC. Would you mind to try configuring the Native PHY to 0xBC to see if the byte ordering still working?

With the right pattern, if you sue BC60, the byte ordering should still work.