FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
4965 Discussions

Cyclone V device has sign addition operation. Can it be implemented by DSP resource

RLi1
Partner
212 Views

Cyclone V device has sign addition operation. Can it be implemented by DSP resource

0 Kudos
1 Reply
CheePin_C_Intel
Employee
79 Views

Hi,

 

If I understand it correctly, you are referring to the sign addition using LPM_ADD_SUB IP. As I look through the IP and user guide, I am unable to locate any specific option to implement this in DSP hard block. Sorry for the inconvenience.

Reply