Cyclone V hardware DMA

[fpga_lac]

Hello,

I want to transfer data from the FPGA to the cyclone V's SDRAM, using the hardware DMA as illustrated in the following figure 

I configured the DMA by the HPS. To handle data transfer, the DMA is equipped with a " peripheral request interface", this interface is connected to the block " Synopsys adapter and clock crossing".

The only information available from the document 'Cyclone V hard processor system technical reference manual' is that this block is controlled by the fpga using the following hand shake signals:

- dma_tx_req_n 

- dma_rx_req_n 

- dma_tx_ack_n 

- dma_rx_ack_n 

- dma_tx_single_n 

- dma_rx_single_n

Is it possible to have technical support on how to control those signals in order to inform the DMA that there is data available on the FPGA side?

Thank you in advance for your support.

[aikeu]

Hi fpga_lac,

There is this dma controller example design link which may help for your use case:

https://github.com/robertofem/CycloneVSoC-examples

Thanks.

Regards,

Aik Eu

[fpga_lac]

​Hi Aik Eu,

Thank you for your answer, I solved the problem.

[aikeu]

Hi fpga_lac,

I will close this thread if there is no further question.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi fpga_lac,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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Thanks.

Regards,

Aik Eu