Cyclone10 GX development kit USB 2.0 packet corruption

[LGonz14]

To whom it may concern,

I'm currently debugging an issue with data packet corruption from the USB 2.0 circuitry using a TeleDyne Lecroy M3x protocol analyzer/exerciser. I was wondering if the USB 2.0 circuitry was ever tested?

[Deshi_Intel]

HI,

Unfortunately I don't see any USB 2.0 IP from Intel FPGA. Hence, I doubt it can be verified.

Typically, user just used the micro USB for dev kit board FPGA JTAG programming function.

Thanks.

Regards,

dlim

[LGonz14]

Hi,

The cyclone 10 gx development kit has a USB 3.1 and USB 2.0 circuit separate from the regular USB 2.0 FPGA JTAG programming function. Please see pages 24 and 25 on the schematics. That's the USB 2.0 circuit I'm referring to. So you're telling me that Intel might have never verified the functionality of this circuit?

[Deshi_Intel]

HI,

Sorry if my explanation is unclear.

Intel did verified USB port on C10 GX dev kit board but just in different way.

Let me clarify

• It's impossible for Intel FPGA to support all different protocol over the world
• Sometime Intel leverage 3rd party design house to support certain IP protocol (For instance, USB is one of the case here)
• For C10 GX dev kit, Intel outsource 3rd party design house (SLS) to provide production test image to validate on board USB port

Therefore from Intel perspective, unfortunately I don't have any reference design nor IP knowledge to help you debug USB issue as USB IP is not supported by Intel FPGA.

My suggestion is feel free to engage SLS directly if you are interested with USB design service solution

• https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/system-level-solutions--inc-.html

Thanks and appreciate your understanding.

Regards,

dlim