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5203 Discussions

Cyclone3 with HSMC data conversion board

Honored Contributor II


I just bought the DSP development kit - Cyclone3 edition (3C120). It comes with an ADC/DAC conversion card that can sample the ADC at 150 MSpS. However the documentation is giving me some problems I hope someone here can help me with... 

The HSMC signal FPGA_CLK_A_P is listed to be on FPGA pin_V10, but I can't select that in the pin planner. 

The signal FPGA_CLK_B_P is on the other hand listed to be on pin_W8 and I can select that in the pin planner. Why can't I select the FPGA_CLK_A_P - is it an error in the documentation? 


Also I have made a test project where I have a 125 MHz input clk, which I put into a PLL in zero delay buffer. The output is send to an altclkctrl instance and send to an output pin (FPGA_CLK_B_P). Then I get a warning: 

Warning: PLL "altpll0:inst|altpll:altpll_component|altpll0_altpll:auto_generated|pll1" output port clk[0] feeds output pin "CLK_out~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance 


Why is the output clk of the FPGA to the HSMC interface not a dedicated clk path? Do I miss something? 


Hope someone can point me in the right direction.
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3 Replies
Honored Contributor II

i have seen problems in the documentation of the conversion card pin locations. although tedious, i would pull up both schematics and verify

Honored Contributor II

Thx, I can see the pinout is different in the two documents.

Honored Contributor II


I've had the same issue with this dev board (actually why i signed up for the forums) There are pin descrepencies between the HSMC reference document PDF and the Dev Board reference document. the DevBoard reference PDF seems to be the correct one so far. Also, if you installed the reference designs, there is one called "cycloneiii_3c120_dev_golden_top" in the examples folder which you can import the pin assigments. This contains all the HSMC pins and are correct (I hope) .  


Also, if you haven't already, make sure you define the IO standard for your clock pin as LVDS and define your clock_bar signal as such:  


(clk_25_out is my pll output. this is copied straight from pin assignments) 


ok clk_25_out i/o standard lvds yes  

ok clk_25_out location pin_g6 yes  

ok clk_25_out(n) location pin_g5 yes 


You can get the latest reference examples/documentation here: