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Honored Contributor I
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CycloneIII FPGA Starter kit DDR clock pins and main oscillator voltage

Hi, 

I am designing a board with a CycloneIII device and some DDR memory. 

 

Having a look to the Cyclone III FPGA starter kit board, I can not quite understand a couple of points: 

 

- The mem_clk pins for the DDR memory are connected to the output pins of the PLL on bank 3 and this looks a sensible choice to me but Altera, in the "External Memory Interface Handbook Volume 2: Device and Pin Planning and board design Guidelines" at page 2-16, suggests: 

 

 

"any differential i/o pin pair (diffout) in the same bank or on the same side as the data pins. you can use either side of the device for wraparound interfaces. mem_clk[0] and mem_clk_n[0] cannot be placed in the same row or column pad group as any of the dq pins." 

 

 

It seems to me that, in the CycloneIII FPGA Starter kit board, the above is violated (CK/CKn are on a differential output pair but they are located on the same row and column of some DQ pins).  

Furthermore, when I compile one of my designs that fits in this Cyclone III FPGA starter kit board and uses the provided DDR chip, I get a couple of the following warning messages: 

 

 

"warning: ck/ckn pin mem_clk_to_and_from_the_ddr has been placed on a pll clkout pin. they should be placed on differential io (diffio) pins only." 

 

 

The same warnings disappear when I move the CK and CK_n to pins M6, N6 which satisfy Altera guidelines. 

 

 

I am wondering whether, in my design, I should follow what Terasic did on the Cyclone III FPGA starter kit board (CK/CKn connected to the PLL output pins) or Altera suggestions (CK/CKn connected on differential IO, which also fixes the Quartus II warning messages)  

 

 

Is there anybody that can help me on this point, please? 

 

 

 

- Another one is : the Cyclone III FPGA Starter kit board uses a 50MHz - 3.3V output oscillator and this signal is connected to pin V9 at bank 3 which is supplied (like all the other banks in the board) with 2.5V supply.  

 

 

Is this ok, having taken into consideration that Altera suggests, for the Cyclone III family, to be careful with the input pins, even recommending series termination resistors at the source ? 

 

 

Thanks in advance for your help. 

 

Michele 

 

 

 

 

 

 

 

 

 

 

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Honored Contributor I
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I decided to have CK/CKn of the DDR directly connected to the PLL output pins in my board, just like the Cyclone III FPGA starter kit board. I still have doubts but, at the end of the day, the Terasic board works fine so, at the moment, this is the safest option. 

 

On the other side, I will use a 2.5V output oscillator at the beginning as it could be easily replaced without any pain. 

 

In the meantime, I had the need to add another DDR chip in the design and another problem has arisen: 

 

I tried to compile a design with 2 DDR controllers and, basically, I did something very very similar to what I found at page 17 of  

"an 462: implementing multiple memory interfacing using the altmemphy megafunction": there is one clock source feeding both refclk inputs of the DDR controllers (this is a SOPC builder request), one of them is a kind of slave, has the "uses clocks from another controller" option ticked so it receives the sysclk (from the other DDR controller) on its shared_sys_clk input.  

The sysclk is the clock for the rest of the system as well. 

 

The SOPC builder is happy with this configuration and completes the generation process successfully. 

 

When I launch the compilation process, from QuartusII I get the following : 

 

"critical warning: pll ddr1:the_ddr1|ddr1_controller_phy:ddr1_controller_phy_inst|ddr1_phy:ddr1_phy_inst|ddr1_phy_alt_mem_phy:ddr1_phy_alt_mem_phy_inst|ddr1_phy_alt_mem_phy_clk_reset:clk|ddr1_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_gqg3:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "pin_ab12

 

I understand this happens because, I am not feeding the "slave" DDR controller PLL (the refclk input) with the input pin it is meant to be fully compensated but I am doing it internally from the clock pin related to the other DDR controller. Am I right? 

 

- Should I connect my external oscillator to both the FPGA pins related to the PLLs I am using and instruct QuartusII in this sense? 

 

- Is it safe to modify the mode of the PLL of the "slave" controller to no-compensated ? (QuartusII compiles with no critical warnings in this case) 

 

Any help is very well wellcomed.  

 

Michele
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Honored Contributor I
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Did this method work for you? Im seeing the same warning: The starter board was used as reference, and it worked fine (I dont even recall seeing the warning crop up...), but trying to use the PLL pins gives me warnings... and I'm worried they may turn into errors in a later version of Quartus... 

 

Thanks!
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Honored Contributor I
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Hi, 

my board will arrive next week. 

I will try to post my progress...if any... 

Michele
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Honored Contributor I
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Hello, 

 

just an update to all of you reading my post. 

 

Today I received my board and I am quite relieved as it seems working fine. So, summarizing my results: 

 

- Using the 2.5V oscillator clocks fine the FPGA device (not really surprisingly as the bank is supplied with 2.5V); I am still wondering why Terasic is using a 3.3V oscillator on their Cyclone III FPGA Starter kit. 

 

- Like Terasic, I connected the mem_clk pins for the DDR memory to the output pins of the PLLs;  

 

- Modifying the mode of the PLL of the "slave" DDR controller to no-compensated removes the critical warning and saves functionality of the system. I can run my DDR memory test program (I write the whole DDR memory chips with a pattern and read it back for verification). 

 

I hope the above is useful. If anybody has different results, please, let me know. 

 

Michele
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