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Valued Contributor III
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CycloneIII Starter Board

(Disclaimer: I am a Nios and Altera Newbie. If anything (or everything) I say is wrong and/or stupid, please let me know). 

 

I recently purchased a CycloneIII Starter Board followed about 3 months later by the Terasic NEEK upgrade kit. So I should have the equivalant to the NEEK straight from Altera. 

 

I have gone through some tutorials, but most of them are centered around "load this file and press some buttons". I dug around a bit and found some "build from scratch" tutorials that walk you through the process of getting a design onto the board. Most are not for the NEEK and so I had to fudge things a bit to get through them.  

 

After learning a bit about the tools, I set out to design my own. Here I am running into trouble. I want to make a Nios Processor that can blast a "hello world" message out of the serial port on the NEEK. 

 

On the daughtercard schematic I trace the RX line from the connector, through the tranceiver, and back through the MAXII device, and out the the HSMC on pin 115. On the Cyclone 3 development board pin 115 on the HSMC connector is HSMC_TX_n10, which appears to lead to pin E18. 

 

Back in Quartus, when I try to connect the RX line to pin E18 (using Pin Planner), I get the following error. 

 

..Error: Can't place pins assigned to pin location Pin_E18 (IOPAD_X53_Y21_N14) 

....Info: Pin uart_rxd is assigned to pin location Pin_E18 (IOPAD_X53_Y21_N14) 

....Info: Pin ~ALTERA_nCEO~ is assigned to pin location Pin_E18 (IOPAD_X53_Y21_N14) 

..Error: Can't fit design in device 

 

I have since figured out that some pins are used for configuration, and cannot be used for anything else. I have tried all the options in the "Assignements...Device Settings...Device...Device and Pin Options" menu of QuartusII to no avail. 

 

Is it possible for me to use the serial port on the NEEK Kit? If so, how do I set up the "configuration"? Are there any "build from scratch" tutorials for the NEEK?
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Valued Contributor III
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asignements->Device options->Device and pin options->Dual purpose pins->see picture 

 

http://users.pandora.be/svhb/device_options.JPG
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Valued Contributor III
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So if I remove that pin as a "Programming Pin", what impact is that down the road. Is that pin needed to configure the device? Can all those other pins be set to "regular IO"? 

 

Do you know how the CycloneIII starter board is supposed to be configured? From what I gather, the choice in configuration in Quartus is dependent on how the chip is wired on the board. But the schematic does not indicate which configuration method they chose and I am still trying to figure out how to determine that.
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Valued Contributor III
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This board doen't need that pin, it is not used whe configuring the device with JTAG. 

 

Since this is a pin that connects to the doughter card you have, it's free to use a a regular I/O. See the altera documentation (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf)on what options you have for ptogramming a cycloneIII and for what specific configuration mode you need this pin. 

 

Stefaan
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Valued Contributor III
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Example projects shipped with CIII starter board are also using regular io setting for all dual purpose pins cause the board needs none of them.

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Valued Contributor III
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What I am trying to do is to bring a project up from scratch. This way I learn what all needs to be done to get things running. I do not like pre-built projects because I feel like they hide too much important stuff. 

 

So I have set out to make a template project that is nothing more than the pin assignments on the NEEK board. No logic inside the part. I almost have this done, but there are a few last straggling errors, and I am a bit befuddled by them. 

 

The errors I get are these... 

 

Error: Following feature(s) of I/O pin FLASH_SRAM_DQ0 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location H3 

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF 

Error: Following feature(s) of I/O pin FLASH_SRAM_DQ1 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location D1 

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF 

Error: Pin FLASH_SRAM_DQ19 is incompatible with I/O bank 1. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V. 

Info: Pin FLASH_CLK in I/O bank 1 uses VCCIO 3.3V 

Info: Pin FLASH_RESET_n in I/O bank 1 uses VCCIO 3.3V 

Info: Pin FLASH_CE_n in I/O bank 1 uses VCCIO 3.3V 

 

For the "Open Drain" error, I have no idea where that is set. I have looked all over for that setting, but I have not found it yet. 

 

For the last error, I have tried adjusting the bank voltage and the pin voltages, and various other settings. But none have been successful. Can anyone shed some light on this. 

 

Thanks in advance for the help. I am sure this is basic stuff, but I am learning a lot. 

 

Attached is my project if you want to take a closer look.
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Valued Contributor III
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Hallo Brian, 

 

I tried to compile your design and found some assignment errors. You assigned incompatible IO standards to some pins,the board is using VCCIO of 2.5V at all banks. Also some dual-purpose pins haven't been set to regular I/O, which is necessary, als already discussed. 

 

After these changes, I get still the reported errors for two pins: 

 

--- Quote Start ---  

Error: Following feature(s) of I/O pin FLASH_SRAM_DQ0 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location H3 

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF 

Error: Following feature(s) of I/O pin FLASH_SRAM_DQ1 has invalid setting(s) in configuration scheme ACTIVE_SERIAL when the pin is placed at pin location D1 

Info: The IO feature 'Open Drain' has invalid setting, it should set to OFF 

--- Quote End ---  

 

The fact, that no Open Drain option is actually set indicates, that we are experiencing a Quartus bug in this case, to my opinion. Also, a basic oddity is this: Although the Starter Board is using AP configuration, you can't set AP configuration in Device Options without generating a shower of errors. The example designs shipped with the Starter Board have their configuration set arbitrarily to AS, seems to be some kind of bug work-around. 

 

Apparently another secret option allows the example design to use the same pins as your design without generating the reported silly open drain error. Perhaps another user knows about, otherwise Altera support must fix the problem. 

 

Regards, 

Frank 

 

P.S.: I found a solution. connecting a bidirectional buffer to the affected pins allowed the design to compile.  

 

By the way, you can expect further exciting experiences when connecting the DDR II pins. I suggest to read thorougly what's been said regarding placement rules and the neccesity to define output enable groups with bidirectional SSTL IO pins.
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Valued Contributor III
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Thank you for the fix. Just to clarify, the buffer you used was the IO buffer in primitives/buffer section of the library. The alt_bidir_buf had other issues, which I did not delve into. 

 

Where should I look for these placement rules? In the Quartus documentation or the CycloneIII device documentation? I am assuming in Quartus.
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Valued Contributor III
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--- Quote Start ---  

The fact, that no Open Drain option is actually set indicates, that we are experiencing a Quartus bug in this case, to my opinion. Also, a basic oddity is this: Although the Starter Board is using AP configuration, you can't set AP configuration in Device Options without generating a shower of errors. The example designs shipped with the Starter Board have their configuration set arbitrarily to AS, seems to be some kind of bug work-around. 

--- Quote End ---  

 

 

The CycloneIII starter board has the MSEL0-3 bits tied to ground. Does this not set up the device for JTAG configuration? This is not an option in Quartus, and I figured that AS was the next closest thing.
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Valued Contributor III
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--- Quote Start ---  

The CycloneIII starter board has the MSEL0-3 bits tied to ground 

--- Quote End ---  

 

Are you using a different board than DK-START-3C25N? It has MSEL wired permanently for AP 2.5V configuration according to the circuit diagram, as necessary for the flash device assembled to the board. JTAG configuration is always possible in addition. 

 

Regarding the buffers connected to overcome the strange open drain issue, I attached the modified project with my previous post, you can check yourself. I think the point is, that something has to be connected to the pin at all. 

 

The pin options for a DDR memory controller are normally set by a script file, it would be sufficient to import it to the design. But it can happen, that you miss this step and then several placement rules in effect with SSTL may be violated. The rule are documented in Cyclone III handbook and also in application notes. If you e.g. would set all DDR pins in the design to the required SSTL-2 standard without some additional definitions, you get a lot of errors. Reviewing the DDR pin assignments in Altera provided example designs, e. g. cycloneIII_3c25_start_niosII_standard can help to understand the requirements.
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