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Altera_Forum
Honored Contributor I
838 Views

DCFIFO and AD9433 problem

Hi to all, 

 

I am currently working on a project using the Alter EP1S25 Development Board. I am sampling a signal using the on-board AD9433 analog-to-digital converter. To check if the sampling is correct i feed the AD9433 output to the input of the on-board DAC904 digital-to-analog converter and view the output of the DAC using an oscilloscope. I want the output of the AD9433 to be fed to a DCFIFO. 

 

Here's what i've done so far: 

1. When the ADC output is connected to the DAC input (without the DCFIFO yet), the DAC output viewed on an oscilloscope has a frequency 230 kHz. This is the expected output. 

 

2. When the ADC output is fed to the DAC input and to the input of the DCFIFO simultaneously, the DAC output viewed on an oscilloscope becomes 760 kHz. 

 

3. When the ADC output is fed to the DCFIFO input only (without the DAC), the data read from the FIFO (and transmitted to a PC) corresponds to a signal with a frequency of 760 kHz. 

 

What could possibly be wrong with the system? I can't think of any reason as of now on why the ADC output changes when the DCFIFO is present. 

 

Thanks in advance. I hope I could fix this soon.
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6 Replies
Altera_Forum
Honored Contributor I
83 Views

Sounds like ADC and DAC are running a different sampling rates (e.g. 50 aand 165 MHz) and are connected to the FIFO without rate conversion. You should think over, what you want to achieve.

Altera_Forum
Honored Contributor I
83 Views

Here's the thing, I'm only using the DAC to see if the ADC output is as expected or not. The write clock of the FIFO is at the same frequency as that of the ADC clock (but shifted by 180 degrees) so I only write every new data coming out of the ADC once. Is there something wrong with this? 

 

The problem is, why would the output of the ADC (as viewed from the output of the DAC) change when the FIFO is connected? 

Is this some kind of loading effect or something? 

Do I need to do some kind of buffering or something with the ADC output? 

 

Thanks guru. Appreciate the reply.
Altera_Forum
Honored Contributor I
83 Views

Unfortunately, i don't understand what you are exactly doing. Can you please tell about the involved ADC and DAC sampling rates and how the FIFO source and sink handshake signals (wrreq, rdreq, full, empty) are connected? 

 

By the way, it's impossible to replay the ADC signal at a different rate continously. If you see a higher DAC output frequency (I assume you actually measure the output signal) than the ADC input signal has, it means that a block of data is repeated multiple times. You should be aware of, if you look sharp on it.
Altera_Forum
Honored Contributor I
83 Views

Sir, 

 

Yes, I am aware that a data block from the ADC will be repeated multiple times at the DAC output if the DAC is running at a faster clock. 

Again, I'm only doing this to check if the output of the ADC is as expected. I know that the ADC output is correct if the DAC output is repeating at 230 kHz. But again, my problem is with the ADC and FIFO connection. I don't really need the DAC. I only use the DAC to check if the ADC is running properly. 

Now the problem is, when I feed the ADC output to the DAC and a FIFO, the DAC output becomes 760 kHz. In other words, the ADC is running properly when connected to the DAC alone but it is not running properly when the ADC is connected to a DAC and a FIFO. 

What is he FIFO doing to the ADC? 

 

Thanks for the reply, appreciate the help
Altera_Forum
Honored Contributor I
83 Views

How are you implementing those connections? 

HDL, schematic or SOPC?
Altera_Forum
Honored Contributor I
83 Views

Schematic connection

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