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DDR2 uniPHY Controller on Stratix IV (EP4SGX230KF40C2N)

Honored Contributor II

Hello everyone, 


I am trying to create a DDR2 uniPHY controller on my Stratix IV DE4, I am using a compilation of altera tutorials to find my way out, but unfortunately am still not able to do it.  


I am able to successfully compile and then program the board with SignalTap II , but when I try to run the software from eclipse am getting the classic ELF error message "Downloading ELF Process failed". I have checked my license and there is no problem. Some google results stands that it might me a pin assignment problem, all pins were assigned according to the board datasheet but I have some doubts about the following pins: 

- afi_clk_out , afi_half_clk_out: were assigned to board clock out pins  

- the memory interface status signals: local_cal_fail, local_cal_success, local_init_done were assigned to GPIO pins  

- local_powerdn_ack were assigned to GPIO pins 

- local_powerdn_req were assigned to GPIO pins 


Furthermore, I have 2 .sof files (one is with "time limitations") both of them have the same ELF problem. 


While am trying to run the software, I also got in the console something like "pausing target processor not responding", does this have any connection to the problem? Could you give me some hints how to track the problem! I am stuck with it for weeks now.
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Honored Contributor II

Am still trying to fix this problem, but at least now I can be sure that the design pins are totally correct. License is also checked  

Also I 've removed the uniPHY controller from the design and then the design worked correctly. Therefore am sure now that the problem is directly connected to the uniPHY. It could be in the sopc design also, nevertheless I had no errors there! 

I will try to track back the warnings hopefully I will find a solution. 


Any hints are always welcome :)
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