12-04-2013 01:58 PM
Hi,I'm trying to deal with both DDR3 A and DDR3 B of the Cyclone V Dev Kit. Has anyone already tried to use both DDR3 A and B in the same design ? I met a problem to find out exact pins for OCT signals. (only pin_ak13, wheras I need two pins). Could you help me please ? Thanks, AC.
12-05-2013 09:11 AM
Hi, we are currently implementing DDR3A & B on the Cyclone V GX dev. board.--- Quote Start --- Has anyone already tried to use both DDR3 A and B in the same design ? I met a problem to find out exact pins for OCT signals. (only pin_ak13, wheras I need two pins). --- Quote End --- You are correct in that the only pin for the OCT signals is PIN_AK13. To solve this you need to go into your QSYS system and in the DDR3 configuration dialogs, you need to enable OCT sharing. Configure one of the DDR3 blocks as Master and the other as slave. The master will have an OCT signal to export and an OCT SHARING conduit that must be wired to the slave DDR3 block's OCT SHARING conduit interface. This should take care of that....
12-05-2013 09:14 AM
Hi,look at the correct xls file to find rzq pins: http://www.altera.com/literature/lit-dp.jsp?category=cyc%205&showspreadsheet=y you can also display "all assignable pins" in the pin planner an then sort them by "special function". you will find rzq pins. if you have problems with calibration blocks look at: http://www.altera.com/support/kdb/solutions/rd02262013_81.html hope it helps.