- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
HI,
mem_CK is the reference clock used to calibrate other DDR3 signal but we don't calibrate mem_CK signal itself.
That's why you see the report shown CK as n/a
Thanks.
Regards,
dlim
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks dlim,
Can I use the SignalTap while the memory interface toolkit is running ?
Trying to find the cause the calibration failure.
Thanks for any hints.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I don't encourage to use signal_tap as both signal_tap and EMIF toolkit are utilizing JTAG connection resource.
Besides, EMIF calibration operates within hard IP only. You can't signal_tap the hard circuit block in FPGA anyway.
Typically EMIF calibration failed due to either EMIF IP setting or board design and connection issue. Don't worry about user logic design part as that only comes later once EMIF calibration passed.
Attached is EMIF calibration debug checklist for your reference.
Thanks.
Regards,
dlim
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You are welcome ! :)

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page