DDR3 SO-DIMM 16G - Calibration fail (external memory interface toolkit) why are the CK signals N/A in the report (ref attached file)

[pzuff1]

Design made with platform designer (example design).

thank you

[Deshi_Intel]

HI,

mem_CK is the reference clock used to calibrate other DDR3 signal but we don't calibrate mem_CK signal itself.

That's why you see the report shown CK as n/a

Thanks.

Regards,

dlim

[pzuff1]

Thanks dlim,

Can I use the SignalTap while the memory interface toolkit is running ?

Trying to find the cause the calibration failure.

Thanks for any hints.

[Deshi_Intel]

Hi,

I don't encourage to use signal_tap as both signal_tap and EMIF toolkit are utilizing JTAG connection resource.

Besides, EMIF calibration operates within hard IP only. You can't signal_tap the hard circuit block in FPGA anyway.

Typically EMIF calibration failed due to either EMIF IP setting or board design and connection issue. Don't worry about user logic design part as that only comes later once EMIF calibration passed.

Attached is EMIF calibration debug checklist for your reference.

Thanks.

Regards,

dlim

[Deshi_Intel]

posted a file.

[pzuff1]

Hi dim, Thank you for your XLS EMIF_calibration doc. => helped me to narrow and solve the troublshouting

[Deshi_Intel]

You are welcome ! :)