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Altera_Forum
Honored Contributor I
1,040 Views

DDR3 Termination scheme

Hi, 

 

In Stratix IV GX FPGA Development Kit Board(EP4SGX230KF40) there are two DDR3 interface.  

In 128 Mbytes DDR3 TOP interface, no termination are used for address and control signals. 

Is it that, as there are no multiple DDR3 components and single DDR3 device will be a point to point connection there is no need for termination for it?  

 

Please suggest. 

 

Regards, 

Sachin
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6 Replies
Altera_Forum
Honored Contributor I
34 Views

I am not sure, but yes, if the wire length is less than 5cm, then no termination is needed.

Altera_Forum
Honored Contributor I
34 Views

Please can I get clear explanation for the above termination scheme. 

 

Regards, 

Sachin
Altera_Forum
Honored Contributor I
34 Views

Basically, if the clk wavelength/4 is longer than a wire of the clk, then no external termination can be used. Again, I am not sure what I am posting, just some overheard stuff.

Altera_Forum
Honored Contributor I
34 Views

The termination as you mean is on board termination? 

As i know, SIV device have ODT(on device termination) feature that can replace the on board termination.
Altera_Forum
Honored Contributor I
34 Views

ODT is usual practice with DDR3.

Altera_Forum
Honored Contributor I
34 Views

hi all!!! 

 

i am developing a board with a cyclone V FPGA and a DDR3 .......... 

 

 

I would like to know if address, comand and control need a ternination escheme, i am using only one memmory DDR3. 

 

i know DDR3 use fly-by termination scheme , but if don´t need i don´t do...... 

 

 

anyone cam help me?? 

 

 

Franz Wagner
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