Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Sushmita
Beginner
131 Views

DDR3 controller soft controller IP on Cyclone V GT Nios example design

Hi,

I am trying to run the example design of Ethernet_main_system using NIOSII in qsys for cyclone V GT board. I have few queries regarding the DDR3 controller IP used in the same:

 

1) The DDR3 controller IP by default used the soft memory controller. Is there any rule/ compulsion to use a soft memory controller while using NIOS (SOFT PROCESSOR)?

 

2) The AFI clock output generated by the IP, should it be connected as input clock to the custom design or any PLL clock output with same clock can do?

 

3) What is the advantage of using Soft controller, if NIOS needs the same?

 

Regards

Sbilg

0 Kudos
2 Replies
MEIYAN_L_Intel
Employee
65 Views

Hi,

 

I am checking the information internally for the first and second question.

For the third question, the advantages of using soft controller is maximum flexibility to choose memory interface and support wider interface. 

For more information, you could refer to document as link below: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01188-hard-memory-con...

 

Thanks

MEIYAN_L_Intel
Employee
65 Views

Hi,

Sorry for late reply.

Upon checking, the queries regarding the DDR3 controller IP as below:

Question:The DDR3 controller IP by default used the soft memory controller. Is there any rule/ compulsion to use a soft memory controller while using NIOS (SOFT PROCESSOR)?

Answer: For rule to use the soft memory controller, you may need to refer to the document as link below: 

https://www.intel.com/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/external-memory/emi_int...

 

Question: The AFI clock output generated by the IP, should it be connected as input clock to the custom design or any PLL clock output with same clock can do?

Answer: AFI_clk output from DDR IP can be used to connect to custom design logic that interact with DDR controller IP

so that both custom design logic and DDR IP is synchronizing (due to using same clock source). It can be said as the AFI_clk output is used as the reference clock for custom design logic. 

Thanks

Reply