DDR3 use from FPGA - DE10-Standard

[DR6]

Hello, 

I am using the Terasic's DE10-Standard Dev-Board (Cyclone V SX SoC—5CSXFC6D6F31C6N) and I wanted to access the DDR3 SDRAM memory directly from the FPGA (No DMA). But I cannot make it work, as I will explain.

I am using the Linux BSP Console provided by Terasic, however I modified the device tree file (.dts & .dtb) to add a reserved-memory block as follows:

reserved-memory {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;
    shared_memory: buffer@20000000 {
        no-map;
        reg = <0x20000000 0x20000000>;
    };
};

Also as part of the configuration I have attached a screenshot of the Platform designer (I am using an Avalon-MM Bidirectional of 64 bits). I will also attach the VHDL code.

Finally, on the Linux side I performed these steps
> mkdir fat
> mount /dev/mmcblk0p1 fat
> cp soc_system.rbf fat/soc_system.rbf
> umount fat
> reboot

(now in u-boot console):

> mw 0xFFC25080 0x0
> fat load mmc 0:1 0x2000000 soc_system.rbf
> fpga load 0 0x2000000 0x700000
> mw 0xFFC2505C 0xA
> mw 0xFFC25080 0xFFFF
> boot

With that said the issue I have detected is that the waitrequest signal of the Avalon MM module remains always high.

Thanks in advanced for any help.

[sstrell · Accepted solution]

I'm not sure that you're coding for waitrequest correctly.  If waitrequest is high when you issue a read or write command, you have to maintain the control signaling until it goes low.  You don't have any code for this situation.  It looks like you're bouncing between the IDLE and READ and WRITE states with the control signals going back and forth between high and low.  You should stay in the IDLE state until waitrequest goes low.

[DR6]

Thanks for the reply. I was reviewing the code after your reply, and with some time perspective (I wrote it some days ago), I also think it is not properly coded. I will definitely take a look at that.