I checked your design and I can see that you are using 150Mhz (half rate) on emif clk. Is it the similar frequency used in your sampling clock in signal tap?
Anyway, sometime time shift is due to the signaltap. As in you are using same frequency on both clk, so it might accidentally shifted. But, if your are not seeing any error/problem then there is nothing to worry about.
I recommend using higher frequency at your sample clock but please make sure it able to close timing.