FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5892 Discussions

DDR4 HILO in S10MX failed initialization

XNguy4
Novice
948 Views

I am using the qts_hilo_ddr4_x72_1066MHz sample project to test the DDR4 HILO in the Stratix 10 MX development kit. I didn't change anything, except upgrading the project from Quartus 18.1 to Quartus 19.4.

After downloading the SOF file in the board, I used SignalTap to observe the signals and realized that DDR4 HILO controller module always returned local_cal_fail = 1.

Screenshot from 2020-03-11 16-58-01.png

Please find the sample project attached and let me know how I can fix the issues.

Thank you very much,

 

 

0 Kudos
6 Replies
NurAida_A_Intel
Employee
831 Views

Hi,

 

Thank you for joining this Intel Community.

 

When you run project from Quartus 18.1, do you facing similar issue?

 

Can you please check on the PLL signal? I suspect the PLL loses lock and this will assert the reset signal until the PLL is locked. The reset signal need to de-assert in order for the controller being enable. Kindly, please check on this two signals.

 

At the meantime, I will recommend you go through the calibration checklist. See if there any item that list in calibration checklist is suspect as the failure’s root cause.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/calibration-checklist.html

 

Hope this helps. Let me know your feedback.

 

Thanks

 

Regards,

Aida

 

 

 

0 Kudos
NurAida_A_Intel
Employee
831 Views

Also please allow me sometime to look into the design and see if I can duplicate the issue from my side. I'll keep ypu updated.

 

 

0 Kudos
XNguy4
Novice
831 Views

Thank you for your quick reply.

I also built the sample project in Quartus Pro 18.1 and got the same problem.

I'm not sure which PLL signal you mentioned as I didn't change anything in the sample project.

You can see the reset_n = 1 with local_reset_done = 1 in the SignalTap

Also, no timing violation was reported in TimeQuest.

Please let me know how I can fix it.

Thanks,

Screenshot from 2020-03-13 16-01-38.png

0 Kudos
XNguy4
Novice
831 Views

Hi Aida,

 

I wonder if you have time to look into the DDR4 HILO problem.

 

Thank you very much,

0 Kudos
s10M
New Contributor I
803 Views

Hello @XNguy4 ,

I am running into a similar problem with my new devkit. 

I was wondering if you managed to solve the problem? 

Thanks a lot. Your help is much appreciated! 

0 Kudos
XNguy4
Novice
800 Views

Hi,

I couldn't solve the problem.

So I gave up this board and move to Xilinx instead.

Thanks.

Reply