I am using the qts_hilo_ddr4_x72_1066MHz sample project to test the DDR4 HILO in the Stratix 10 MX development kit. I didn't change anything, except upgrading the project from Quartus 18.1 to Quartus 19.4.
After downloading the SOF file in the board, I used SignalTap to observe the signals and realized that DDR4 HILO controller module always returned local_cal_fail = 1.
Please find the sample project attached and let me know how I can fix the issues.
Thank you very much,
Thank you for joining this Intel Community.
When you run project from Quartus 18.1, do you facing similar issue?
Can you please check on the PLL signal? I suspect the PLL loses lock and this will assert the reset signal until the PLL is locked. The reset signal need to de-assert in order for the controller being enable. Kindly, please check on this two signals.
At the meantime, I will recommend you go through the calibration checklist. See if there any item that list in calibration checklist is suspect as the failure’s root cause.
Hope this helps. Let me know your feedback.
Thank you for your quick reply.
I also built the sample project in Quartus Pro 18.1 and got the same problem.
I'm not sure which PLL signal you mentioned as I didn't change anything in the sample project.
You can see the reset_n = 1 with local_reset_done = 1 in the SignalTap
Also, no timing violation was reported in TimeQuest.
Please let me know how I can fix it.