客户目前板子上做的 DDR4(SODIMM 72bit) ,当初做管脚验证的工程都可以编译通过，并且已经制版。
由于成本问题，客户想更换DDR4 厂家 ，接口还是SODIMM。现在修改了DDR4 IP (SODIMM 64bit) ，但是软件无法Fitter通过，请问这个无法Fitter 的原因是什么？
客户目前布局在 2k ，2l ,2m,2n 4个bank 里面，其中2l 是地址线，2k ,2m,2n 是数据线。
附件中我会把72bit 的工程，64bit 的工程上传给你，请协助分析一下，谢谢！
Thank you for joining this Intel Community.
I am sorry but I didn't received any attachment as per mentioned. Can you help to re-attach so that I can take a closer look to your issue.
Thank you .
Thanks for sharing the designs. Please allow me sometime to look into the design. I shall come back to you with findings.
Thank you for your patience.
Please accept my apology for the delay in response due to public holiday in my region.
I've compiled your project and see the fitter error. Below is what I’ve been analyzed.
1) Top level file:
a) s10_ddr4_top.v = 72 bits --> inout wire [71:0] mem_dq,
b) ddr4_ip.v = 64bits --> inout wire [63:0] mem_dq
2) Assignment Editor:
Example as below.
It worked for me in a simplified example design test case project. Please try it for your your project pinout and let me know if it works OK. Hope this helps.😊
I am sorry for the delay in response due to current workload.
Proper design practice is to verify fitter placement first before proceed to board design.
Normally it’s fine to reduce DQ width and by right it shouldn’t hit fitter error
Sorry I couldn’t be more helpful. This is the best I can do. Let me know if there is any help needed.