FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
4965 Discussions

DE III problem witch Voltage of the I/O pins

Altera_Forum
Honored Contributor I
771 Views

Hi. 

I’m developing a project in the DE3 and I’m having a problem with the voltage of the GPIO Pins.  

To describe my application, It consists basically of use the switches and the dipswitches to control the value of the GPIO Pins. Above, I give an example: 

GPIO_D11<= DIP_SW_4 

GPIO_D12<=SW_1 

GPIO_D13<=SW_2 

I have all the compilation ok and so the download to the board. But, as I was having some trouble with my other application that uses those signals, I start to measure the GPIO pins with an multimeter. Then, I realize that when I put most of my signals in ON, I have an decrease of the value of the Voltage of some of the pins. 

For example: when I have the SW_1 and the SW_2 in OFF, and the DIP_SW_4 in ON, the voltage of the GPIO_D11 is 3,19 Vdc; 

But when I have the SW_1 and the SW_2 in ON, and the DIP_SW_4 in ON, the voltage of the GPIO_D11 is only 2,42 Vdc; 

Does anyone know what could be happening? 

I’m using the Quartus II 8.0. 

Thanks for the help!!!!!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
63 Views

I guess the lower voltage on GPIO probably means you have some design issue in the connections outside fpga. For example another signal is driving gpio or excessive current is being drawn from fpga output. 

Are gpios connected to anything?  

Can you also check gpio with an oscilloscope? Maybe the signal is not stable, because some switches configurations introduce an abnormal modulation; since the multimeter is slow, it measures the mean value and you simply see a lower voltage.
Reply